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| 32bit TX System RISC TX19A Family TMP19A64C1DXBG Rev1.1 2007.March.16 TMP19A64C1DXBG Contents TMP19A64C1DXBG 1. Overview and Features 2. Pin Layout and Pin Functions 3. Processor Core 4. Memory Map 5. Clock/Standby Control 6. Interrupts 7. Input/Output Ports 8. External Bus Interface 9. Chip Selector and Wait Contoroller 10. DMA Controller (DMAC) 11. 16-bit Timer /Event COunters (TMRB) 12. 32-bit Timer (TMRC) 13. Serial Channel (SIO) 14. Serial Bus Interface (SBI) 15. Analog/Digital Converter 16. Watchdog Timer (Runaway Detection Timer) 17. Backup Module (Clock Timer ,Backup RAM) 18. Key-on Wakeup 19. ROM Correction Function 20. Security Function 21. Table of Special Function Registers 22. Electrical Characteristics 23. Notations, Precautions and Restrictions TMP19A64(rev1.1)-1 TMP19A64C1D 32-bit RISC Microprocessor - TX19 Family TMP19A64C1DXBG 1. Overview and Features The TX19 family is a high-performance 32-bit RISC processor series that TOSHIBA originally developed by integrating the MIPS16TMASE (Application Specific Extension), which is an extended instruction set of high code efficiency. TMP19A64 is a 32-bit RISC microprocessor with a TX19A processor core and various peripheral functions integrated into one package. It can operate at low voltage with low power consumption. Features of TMP19A64 are as follows: (1) TX19A processor core 1) Improved code efficiency and operating performance have been realized through the use of two ISA (Instruction Set Architecture) modes - 16- and 32-bit ISA modes. * * 2) The 16-bit ISA mode instructions are compatible with the MIPS16e-TX instructions of superior code efficiency at the object level. The 32-bit ISA mode instructions are compatible with the TX39 instructions of superior operating performance at the object level. Both high performance and low power consumption have been achieved. RESTRICTIONS ON PRODUCT USE * The information contained herein is subject to change without notice. 021023_D 070122EBP * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C * The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S TMP19A64(rev1.1)1-1 TMP19A64C1D High performance * * * * * * * 3) * * * Almost all instructions can be executed with one clock. High performance is possible via a three-operand operation instruction. 5-stage pipeline Built-in high-speed memory DSP function: A 32-bit multiplication and accumulation operation can be executed with one clock. Optimized design using a low power consumption library Standby function that stops the operation of the processor core Independency of the entry address Automatic generation of factor-specific vector addresses Automatic update of interrupt mask levels Low power consumption High-speed interrupt response suitable for real-time control (2) On Chip program memory and data memory Product name TMP19A64F20AXBG TMP19A64C1DXBG On chip ROM 2 Mbytes (Flash) 1.5 Mbytes On chip RAM 64 Kbytes 56 Kbytes * * * * * * * * * * * ROM correction function: 1 word x 8 blocks, 8 words x 4 blocks Backup RAM: 512 bytes 16-Mbyte off-chip address for code and date External data bus: Separate bus/multiplexed bus Chip select/wait controller : Dynamic bus sizing for 8- and 16-bit widths ports. : 6 channels : 8 channels : 11 channels (3) External memory expansion (4) DMA controller (5) 16-bit timer 16-bit interval timer mode 16-bit event counter mode 16-bit PPG output Event capture function Data to be transferred to internal memory, internal I/O, external memory, and external I/O 2-phase pulse input counter function (1 channel assigned to perform this function): Multiplication-by-4 mode 32-bit input capture register 32-bit compare register 32-bit time base timer : 4 channels : 10 channels : 1 channel : 1 channel or synchronous mode can be selected. (6) 32-bit timer * * * (7) Clock timer (8) General-purpose serial interface: 7 channels * Either UART mode TMP19A64(rev1.1)1-2 TMP19A64C1D (9) Serial bus interface * * * * * * * (11) (12) * * * 2 : 1 channel : 24 channels Either I C bus mode or clock synchronous mode can be selected Conversion speed: 54 clocks (7.85 s@54 MHz) Start by an internal timer trigger Fixed channel/scan mode Single/repeat mode High-priority conversion mode Timer monitor function Watchdog timer Interrupt source CPU: 2 factors ............. software interrupt instruction Internal: 50 factors....... The order of precedence can be set over 7 levels (except the watchdog timer interrupt). External: 20 factors...... The order of precedence can be set over 7 levels (except the NMI interrupt). Because 8 factors are associated with KWUP, the number of interrupt factors is one. : 1 channel (10) 10-bit A/D converter with (S/H) (13) 209 pins Input/output ports (14) Standby mode * * * * 4 standby modes (IDLE, SLEEP, STOP and BACKUP) On-chip PLL (multiplication by 4) Clock gear function: The high-speed clock can be divided into 8/8, 7/8, 6/8, 5/8, 4/8, 2/8 or 1/8. Sub-clock: SLOW, SLEEP and BACKUP modes (32.768 kHz) (15) Clock generator (16) Endian: Bi-endian (big-endian/little-endian) (17) Maximum operating frequency * 54 MHz (PLL multiplication) Core: 1.35 V to 1.65 V I/O: 1.65 V to 3.3 V ADC: 2.7 V to 3.3 V Backup block : 2.3 V to 3.3 V (under normal operating conditions) : 1.8 V to 3.3 V (in BACKUP mode) (19) Package * P-FBGA281 (13 mm x 13 mm, 0.65 mm pitch) (18) Operating voltage range TMP19A64(rev1.1)1-3 TMP19A64C1D TX19 Processor Core TX19A CPU MAC 1.5-Mbyte Flash EJTAG 56-Kbyte RAM ROM correction DMAC (8ch) INTC Backup block CG EBIF Clock timer (1ch) Backup RAM (512 bytes) I/O bus I/F PORT0 to PORT6 (also function as external bus I/F) PORT7 to PORT9 (also function to receive ADC inputs) PORTA to PORTK, PORTO (also function as functional pins) 16-bit TMRB 0 to A (11ch) 32-bit TMRC TBT (1ch) 32-bit TMRC Input Capture 0 to 3 (4ch) 32-bit TMRC Compare 0 to 9 (10ch) 10-bit ADC (24ch) SIO/UART 0 to 6 (7ch) I2C/SIO (1ch) PORTL to PORTN PORTP to PORTQ (General-purpose ports) KWUP 0 to 7 (8ch) WDT Fig. 1-1 TMP19A64C1DXBG Block Diagram TMP19A64(rev1.1)1-4 TMP19A64C1D 2. 2.1 Pin Layout and Pin Functions Pin Layout Fig. 2.1.1 shows the pin layout of TMP19A64. Fig. 2.1.1 Pin Layout Diagram (P-FBGA281) A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 T1 U1 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 T2 U2 V2 A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 M3 N3 P3 R3 T3 U3 V3 A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 P4 R4 T4 U4 V4 A5 B5 C5 D5 E5 F5 G5 H5 J5 K5 L5 M5 N5 P5 R5 T5 U5 V5 P6 R6 T6 U6 V6 G6 H6 J6 K6 L6 M6 N7 P7 R7 T7 U7 V7 N8 P8 R8 T8 U8 V8 N9 P9 R9 T9 U9 V9 N10 N11 N12 P10 P11 A6 B6 C6 D6 E6 A7 B7 C7 D7 E7 F7 A8 B8 C8 D8 E8 F8 A9 B9 C9 D9 E9 F9 A10 A11 B10 B11 A12 A13 A14 A15 A16 A17 B12 B13 B14 B15 B16 B17 B18 C10 C11 C12 C13 C14 C15 C16 C17 C18 D10 D11 D12 D13 D14 D15 D16 D17 D18 E10 E11 F10 F11 E12 E13 E14 E15 E16 E17 E18 F12 F14 F15 F16 F17 F18 G13 G14 G15 G16 G17 G18 H13 H14 H15 H16 H17 H18 J13 J14 J15 J16 J17 J18 K13 K14 K15 K16 K17 K18 L13 L14 L15 L16 L17 L18 M13 M14 M15 M16 M17 M18 N14 N15 N16 N17 N18 P12 P13 P14 P15 P16 P17 P18 R10 R11 R12 R13 R14 R15 R16 R17 R18 T10 T11 T12 T13 T14 T15 T16 T17 T18 U10 U11 U12 U13 U14 U15 U16 U17 U18 V10 V11 V12 V13 V14 V15 V16 V17 Table 2.1.2 shows the pin numbers and names of TMP19A64. Table 2.1.2 Pin Numbers and Names (1 of 2) Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Pin name N.C. VREFL P90/AN16 P93/AN19 P80/AN8 P83/AN11 P70/AN0 P74/AN4 PO7/SCLK6/CTS6 PL2 PO6/RXD6 PO0/INT0 Pin No. A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 Pin name PN2 PN0 PM5 PM1 X2 AVCC31 VREFH P91/AN17 P94/AN20 P81/AN9 P84/AN12 P71/AN1 Pin No. B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 Pin name P75/AN5 PL0 PL3 PO5/TXD6 PO1/INT1 PN3 PN1 PM4 PM0 CVSS/BVSS X1 PCST0 (EJTAG) Pin No. C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 Pin name PCST3 (EJTAG) P92/AN18 P95/AN21 P82/AN10 P85/AN13 P72/AN2 AVSS PL1 PL4 PO4/INT4 PN6 PN4 Pin No. C14 C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 Pin name PM7 PM3 PK3/KEY3 CVCC15 XT2 TDO (EJTAG) PCST2 (EJTAG) DINT (EJTAG) DVCC15 P96/AN22 P86/AN14 P73/AN3 TMP19A64(rev1.1)2-1 TMP19A64C1D Table 2.1.1 Pin Numbers and Names (2 of 2) Pin No. D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 F1 F2 F3 F4 F5 F7 F8 F9 F10 F11 F12 F14 F15 F16 F17 BUPMD P42/CS2 P43/CS3 DVCC33 Pin name DVCC15 DVSS PL5 PO3/INT3 PN7 PN5 PM2 DVCC34 PK2/KEY2 PK4/KEY4 XT1 DCLK (EJTAG) PCST1 (EJTAG) TRST (EJTAG) PCST4 (EJTAG) ENDIAN P97/AN23 P87/AN15 P76/AN6 P77/AN7 PL6 PL7 PM6 PK6/KEY6 PK5/KEY5 BVCC PK1/KEY1 PK0/KEY0 DVCC15 DVSS TMS (EJTAG) EJE (EJTAG) BUSMD BOOT AVSS AVSS AVCC32 DVCC34 PO2/INT2 DVSS Pin No. F18 G1 G2 G3 G4 G5 G6 G13 G14 G15 G16 G17 G18 H1 H2 H3 H4 H5 H6 H13 H14 H15 H16 H17 H18 J1 J2 J3 J4 J5 J6 J13 J14 J15 J16 J17 J18 K1 K2 K3 K4 K5 K6 K13 Pin name P46/SCOUT RESET TDI (EJTAG) FVCC15 DVSS TOVR/TSTA (EJTAG) BW0 PK7/KEY7 BRESET P41/CS1 P37/ALE P35/BUSAK FVCC15 NMI DVCC31 PP7/TPD7 (EJTAG) BW1 PLLOFF TCK (EJTAG) TEST1 P31/WR P32/HWR P33/WAIT/RDY P30/RD P40/CS0 PP2/TPD2 (EJTAG) PP3/TPD3 (EJTAG) PP4/TPD4 (EJTAG) PP5/TPD5 (EJTAG) PP6/TPD6 (EJTAG) FVCC15 DVSS P47 N.C. P44/CS4 P36/ R/W P34/BUSRQ PP0/TPD0 (EJTAG) PP1/TPD1 (EJTAG) PQ5/TPD5/TPC5 (EJTAG) PQ6/TPD6/TPC6 (EJTAG) DVSS DVSS TEST2 Pin No. K14 K15 K16 K17 K18 L1 L2 L3 L4 L5 L6 L13 L14 L15 L16 L17 L18 M1 M2 M3 M4 M5 M6 M13 M14 M15 M16 M17 M18 N1 N2 N3 N4 N5 N7 N8 N9 N10 N11 N12 N14 N15 N16 N17 Pin name PI1/INT1 PI3/INT3 PI4/INT4 DVCC30 PI2/INT2 FVCC3 PQ1/TPD1/TPC1 (EJTAG) PQ2/TPD2/TPC2 (EJTAG) PQ3/TPD3/TPC3 (EJTAG) PE6/INTA PE7/INTB P13/D11/AD11/A11 P17/D15/AD15/A15 FVCC15 PI0/INT0 P45/CS5 PJ3/DACK3 PQ0/TPD0/TPC0 (EJTAG) PQ7/TPD7/TPC7 (EJTAG) PQ4/TPD4/TPC4 (EJTAG) PE3 PA7/TB3OUT DVCC32 P06/D6/AD6 P07/D7/AD7 DVSS PJ0/DREQ2 PJ2/DREQ3 PJ1/DACK2 PE5 PE0/TXD5 PE2/SCLK5/CTS5 PE1/RXD5 PA6/TB2OUT DVSS PD7/INT9 DVCC15 DVSS P56/A6 DVSS P27/A23/A7/A23 P15/D13/AD13/A13 TEST3 P16/D14/AD14/A14 Pin No. N18 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 T1 T2 T3 T4 T5 T6 T7 Pin name P14/D12/AD12/A12 PE4 PA2/TB0OUT PA3/TB1IN0/INT7 PA4/TB1IN1/INT8 PA5/TB1OUT PB6/TBAIN0 PG2/TC2IN PD6/SCLK4/CTS4 PC2/SCLK0/CTS0 PC5/SCLK1/CTS1 P52/A2 P62/A10 P65/A13 P26/A22/A6/A22 P02/D2/AD2 P10/D8/AD8/A8 P12/D10/AD10/A10 P11/D9/AD9/A9 PA0/TB0IN0/INT5 PA1/TB0IN1/INT6 PF3/DREQ2 PF4/DACK2 PF7/TBTIN PG7/TCOUT3 PG4/TCOUT0 PD5/RXD4 PC1/RXD0 PC4/RXD1 PH3/TCOUT7 P51/A1 P57/A7 P66/A14 P25/A21/A5/A21 P03/D3/AD3 P04/D4/AD4 P05/D5/AD5 PB0/TB4OUT PB1/TB5OUT PB2/TB6OUT PF2/SCK PF6/DACK3 PG5/TCOUT1 PD3/SCLK3/CTS3 Pin No. T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 Pin name PD4/TXD4 PC0/TXD0 PC3/TXD1 PH4/TCOUT8 PH6 P53/A3 P61/A9 P21/A17/A1/A17 P23/A19/A3/A19 P00/D0/AD0 P01/D1/AD1 PB4/TB8OUT PB3/TB7OUT PB7/TBAIN1 PF1/SI/SCL PF5/DREQ3 PG1/TC1IN PD2/RXD3 DVCC32 PC7/RXD2 PH1/TCOUT5 PH5/TCOUT9 P50/A0 P55/A5 DVCC33 P64/A12 P20/A16/A0/A16 P24/A20/A4/A20 FVCC3 PB5/TB9OUT PG0/TC0IN PF0/SO/SDA PG3/TC3IN PG6/TCOUT2 PD1/TXD3 PD0/SCLK2/CTS2 PC6/TXD2 PH2/TCOUT6 PH0/TCOUT4 PH7 P54/A4 P60/A8 P63/A11 P67/A15 P22/A18/A2/A18 TMP19A64(rev1.1)2-2 TMP19A64C1D 2.2 Pin Names and Functions Table 2.2.1 shows the names and functions of input/output pins. Table 2.2.1 Pin Names and Functions (1 of 6) Pin name P00-P07 D0-D7 AD0-AD7 P10-P17 D8-D15 AD8-AD15 A8-A15 P20-P27 A16-A23 A0-A7 A16-A23 P30 RD P31 WR P32 HWR P33 WAIT RDY P34 BUSRQ P35 BUSAK P36 R/W P37 ALE P40 CS0 P41 CS1 P42 CS2 P43 CS3 P44 CS4 P45 CS5 P46 SCOUT P47 P50-P57 A0-A7 P60-P67 A8-A15 Number of pins 8 Input or output Input/output Input/output Input/output Input/output Input/output Input/output Output Input/output Output Output Output Output Output Output Output Input/output Output Input/output Input Input Input/output Input Input/output Output Input/output Output Input/output Output Input/output Output Input/output Output Input/output Output Input/output Output Input/output Output Input/output Output Input/output Output Input/output Input/output Output Input/output Output Function Port 0: Input/output port that allows input/output to be set in units of bits Data (lower): Data buses 0 to 7 (separate bus mode) Address data (lower): Address data buses 0 to 7 (multiplexed bus mode) Port 1: Input/output port that allows input/output to be set in units of bits Data (upper): Data buses 8 to 15 (separate bus mode) Address data (upper): Address data buses 8 to 15 (multiplexed bus mode) Address: Address buses 8 to 15 (multiplexed bus mode) Port 2: Input/output port that allows input/output to be set in units of bits Address: Address buses 16 to 23 (separate bus mode) Address: Address buses 0 to 7 (multiplexed bus mode) Address: Address buses 16 to 23 (multiplexed bus mode) Port 30: Port used exclusively for output Read: Strobe signal for reading external memory Port 31: Port used exclusively for output Write: Strobe signal for writing data of D0 to D7 pins Port 32: Input/output port (with pull-up) Write upper-pin data: Strobe signal for writing data of D8 to D15 pins Port 33: Input/output port (with pull-up) Wait: Pin for requesting CPU to put a bus in a wait state Ready: Pin for notifying CPU that a bus is ready Port 34: Input/output port (with pull-up) Bus request: Signal requesting CPU to allow an external master to take the bus control authority Port 35: Input/output port (with pull-up) Bus acknowledge: Signal notifying that CPU has released the bus control authority in response to BUSRQ Port 36: Input/output port (with pull-up) Read/write: "1" shows a read cycle or a dummy cycle. "0" shows a write cycle. Port 37: Input/output port Address latch enable (address latch is enabled only if access to external memory is taking place) Port 40: Input/output port (with pull-up) Chip select 0: "0" is output if the address is in a designated address area. Port 41: Input/output port (with pull-up) Chip select 1: "0" is output if the address is in a designated address area. Port 42: Input/output port (with pull-up) Chip select 2: "0" is output if the address is in a designated address area. Port 43: Input/output port (with pull-up) Chip select 3: "0" is output if the address is in a designated address area. Port 44: Input/output port (with pull-up) Chip select 4: "0" is output if the address is in a designated address area. Port 45: Input/output port (with pull-up) Chip select 5: "0" is output if the address is in a designated address area. Port 46: Input/output port System clock output: Selectable between high- and low-speed clock outputs, as in the case of CPU Port 47: Input/output port Port 5: Input/output port that allows input/output to be set in units of bits Address: Address buses 0 to 7 (separate bus mode) Port 6: Input/output port that allows input/output to be set in units of bits Address: Address buses 8 to 15 (separate bus mode) 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 TMP19A64(rev1.1)2-3 TMP19A64C1D Table 2.2.1 Pin Names and Functions (2 of 6) Pin name P70-P77 AN0-AN7 P80-P87 AN8-AN15 P90-P97 AN16-AN23 PA0 TB0IN0 INT5 PA1 TB0IN1 INT6 PA2 TB0OUT PA3 TB1IN0 INT7 PA4 TB1IN1 INT8 PA5 TB1OUT PA6 TB2OUT PA7 TB3OUT PB0 TB4OUT PB1 TB5OUT PB2 TB6OUT PB3 TB7OUT PB4 TB8OUT PB5 TB9OUT PB6 TBAIN0 PB7 TBAIN1 Number of pins 8 8 8 1 Input or output Input Input Input Input Input Input Input/output Input Input Input/output Input Input Input/output Output Input/output Input Input Input/output Input Input Input/output Output Input/output Output Input/output Output Input/output Output Input/output Output Input/output Output Input/output Output Input/output Output Input/output Output Input/output Input Input/output Input Port 7: Port used exclusively for input Analog input: Input from A/D converter Port 8: Port used exclusively for input Analog input: Input from A/D converter Port 9: Port used exclusively for input Analog input: Input from A/D converter Port A0: Input/output port 16-bit timer 0 input 0: For inputting the count/capture trigger of a 16-bit timer 0 Interrupt request pin 5: Selectable between "H" level, "L" level, rising edge, and falling edge Input pin with Schmitt trigger Port A1: Input/output port 16-bit timer 0 input 1: For inputting the count/capture trigger of a 16-bit timer 0 Interrupt request pin 6: Selectable "H" level, "L" level, rising edge and falling edge Input pin with Schmitt trigger Port A2: Input/output port 16-bit timer 0 output: 16-bit timer 0 output pin Port A3: Input/output port 16-bit timer 1 input 0: For inputting the count/capture trigger of a 16-bit timer 1 Interrupt request pin 7: Selectable between "H" level, "L" level, rising edge and falling edge Input pin with Schmitt trigger Port A4: Input/output port 16-bit timer 1 input 1: For inputting the count/capture trigger of a 16-bit timer 1 Interrupt request pin 8: Selectable between "H" level, "L" level, rising edge and falling edge Input pin with Schmitt trigger Port A5: Input/output port 16-bit timer 1 output: 16-bit timer 1 output pin Port A6: Input/output port 16-bit timer 2 output: 16-bit timer 2 output pin Port A7: Input/output port 16-bit timer 3 output: 16-bit timer 3 output pin Port B0: Input/output port 16-bit timer 4 output: 16-bit timer 4 output pin Port B1: Input/output port 16-bit timer 5 output: 16-bit timer 5 output pin Port B2: Input/output port 16-bit timer 6 output: 16-bit timer 6 output pin Port B3: Input/output port 16-bit timer 7 output: 16-bit timer 7 output pin Port B4: Input/output port 16-bit timer 8 output: 16-bit timer 8 output pin Port B5: Input/output port 16-bit timer 9 output: 16-bit timer 9 output pin Port B6: Input/output port 16-bit timer A input 0: for inputting the count/capture trigger of a 16-bit timer A 2-phase pulse counter input 0 Port B7: Input/output port 16-bit timer A input 1: For inputting the count/capture trigger of a 16-bit timer A 2-phase pulse counter input 1 Function 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TMP19A64(rev1.1)2-4 TMP19A64C1D Table 2.2.1 Pin Names and Functions (3 of 6) Pin name PC0 TXD0 PC1 RXD0 PC2 SCLK0 CTS0 PC3 TXD1 PC4 RXD1 PC5 SCLK1 CTS1 PC6 TXD2 PC7 RXD2 PD0 SCLK2 CTS2 PD1 TXD3 PD2 RXD3 PD3 SCLK3 CTS3 PD4 TXD4 PD5 RXD4 PD6 SCLK4 CTS4 PD7 INT9 Number of pins 1 1 1 Input or output Input/output Output Input/output Input Input/output Input/output Input Input/output Output Input/output Input Input/output Input/output Input Input/output Output Input/output Input Input/output Input/output Input Input/output Output Input/output Input Input/output Input/output Input Input/output Output Input/output Input Input/output Input/output Input Input/output Input Function Port C0: Input/output port Sending serial data 0: Open drain output pin depending on the program used Port C1: Input/output port Receiving serial data 0 Port C2: Input/output port Serial clock input/output 0 Ready to send serial data 0 (Clear To Send): Open drain output pin depending on the program used Port C3: Input/output port Sending serial data 1: Open drain output pin depending on the program used Port C4: Input/output port Receiving serial data 1 Port C5: Input/output port Serial clock input/output 1 Ready to send serial data 1 (Clear To Send): Open drain output pin depending on the program used Port C6: Input/output port Sending serial data 2: Open drain output pin depending on the program used Port C7: Input/output port Receiving serial data 2 Port D0: Input/output port Serial clock input/output 2 Ready to send serial data 2 (Clear To Send): Open drain output pin depending on the program used Port D1: Input/output port Sending serial data 3: Open drain output pin depending on the program used Port D2: Input/output port Receiving serial data 3 Port D3: Input/output port Serial clock input/output 3 Ready to send serial data 3 (Clear To Send): Open drain output pin depending on the program used Port D4: Input/output port Sending serial data 4: Open drain output pin depending on the program used Port D5: Input/output port Receiving serial data 4 Port D6: Input/output port Serial clock input/output 4 Ready to send serial data 4 (Clear To Send): Open drain output pin depending on the program used Port D7: Input/output port Interrupt request pin 9: Selectable between "H" level, "L" level, rising edge and falling edge Input pin with Schmitt trigger 1 1 1 1 1 1 1 1 1 1 1 1 1 TMP19A64(rev1.1)2-5 TMP19A64C1D Table 2.2.1 Pin Names and Functions (4 of 6) Pin name PE0 TXD5 PE1 RXD5 PE2 SCLK5 CTS5 PE3-PE5 PE6 INTA PE7 INTB PF0 SO SDA Number of pins 1 1 1 Input or output Input/output Output Input/output Input Input/output Input/output Input Input/output Input/output Input Input/output Input Input/output Output Input/output Function Port E0: Input/output port Sending serial data 5: Open drain output pin depending on the program used Port E1: Input/output port Receiving serial data 5 Port E2: Input/output port Serial clock input/output 5 Ready to send serial data 5 (Clear To Send): Open drain output pin depending on the program used Ports E3 to E5: Input/output ports that allow input/output to be set in units of bits Port E6: Input/output port Interrupt request pin A: Selectable between "H" level, "L" level, rising edge, and falling edge Input pin with Schmitt trigger Port E7: Input/output port Interrupt request pin B: Selectable between "H" level, "L" level, rising edge, and falling edge Input pin with Schmitt trigger Port F0: Input/output port Pin for sending data if the serial bus interface operates in the SIO mode Pin for sending and receiving data if the serial bus interface operates in the I2C mode Open drain output pin depending on the program used. Input with Schmitt trigger Port F1: Input/output port Pin for receiving data if the serial bus interface operates in the SIO mode Pin for inputting and outputting a clock if the serial bus interface operates in the I2C mode Open drain output pin depending on the program used Input with Schmitt trigger Port F2: Input/output port Pin for inputting and outputting a clock if the serial bus interface operates in the SIO mode Port F3: Input/output port DMA request signal 2: For inputting the request to transfer data by DMA from an external I/O device to DMAC2 Port F4: Input/output port DMA acknowledge signal 2: Signal showing that DREQ2 has acknowledged a DMA transfer request Port F5: Input/output port DMA request signal 3: For inputting the request to transfer data by DMA from an external I/O device to DMAC3 Port F6: Input/output port DMA acknowledge signal 3: Signal showing that DREQ3 has acknowledged a DMA transfer request Port F7: Input/output port 32-bit time base timer input: For inputting the count for 32-bit time base timer Ports G0 to G3: Input/output ports that allow input/output to be set in units of bits For inputting the capture trigger for 32-bit timer Ports G4 to G7: Input/output ports that allow input/output to be set in units of bits Outputting 32-bit timer if the result of a comparison is a match Ports H0 to H5: Input/output ports that allow input/output to be set in units of bits Outputting 32-bit timber if the result of a comparison is a match Ports H6 to H7: Input/output ports that allow input/output to be set in units of bits Port I0: Input/output port Interrupt request pin 0: Selectable between "H" level, "L" level, rising edge and falling edge Input pin with Schmitt trigger Port I1: Input/output port Interrupt request pin 1: Selectable between "H" level, "L" level, rising edge and falling edge Input pin with Schmitt trigger Port I2: Input/output port Interrupt request pin 2: Selectable between "H" level, "L" level, rising edge and falling edge Input pin with Schmitt trigger 3 1 1 1 PF1 SI SCL 1 Input/output Input Input/output PF2 SCK PF3 DREQ2 PF4 DACK2 PF5 DREQ3 PF6 DACK3 PF7 TBTIN PG0-PG3 TC0IN-TC3IN PG4-PG7 TCOU0-TCOUT3 PH0-PH5 TCOU4-TCOUT9 PH6-PH7 PI0 INT0 PI1 INT1 PI2 INT2 1 1 Input/output Input/output Input/output Input Input/output Output Input/output Input Input/output Output Input/output Input Input/output Input Input/output Output Input/output Output Input/output Input/output Input Input/output Input Input/output Input 1 1 1 1 4 4 6 2 1 1 1 TMP19A64(rev1.1)2-6 TMP19A64C1D Table 2.2.1 Pin Names and Functions (5 of 6) Pin name PI3 INT3 PI4 INT4 PJ0 DREQ2 PJ1 DACK2 PJ2 DREQ3 PJ3 DACK3 PK0-PK7 KEY0-KEY7 PL0-PL7 PM0-PM7 PN0-PN7 PO0 INT0 PO1 INT1 PO2 INT2 PO3 INT3 PO4 INT4 PO5 TXD6 PO6 RXD6 PO7 SCLK6 CTS6 PP0-PP7 TPD0-TPD7 PQ0-PQ7 TPC0-TPC7 TPD0-TPD7 Number of pins 1 Input or output Input/output Input Input/output Input Input/output Input Input/output Output Input/output Input Input/output Output Input/output Input Input/output Input/output Input/output Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Output Input/output Input Input/output Input/output Input Input/output Output Input/output Output Output Function Port I3: Input/output port Interrupt request pin 3: Selectable between "H" level, "L" level, rising edge and falling edge Input pin with Schmitt trigger Port I4: Input/output port Interrupt request pin 4: Selectable between "H" level, "L" level, rising edge and falling edge Input pin with Schmitt trigger Port J0: Input/output port DMA request signal 2: For inputting the request to transfer data by DMA from an external I/O device to DMAC2 Port J1: Input/output port DMA acknowledge signal 2: Signal showing that DREQ2 has acknowledged a DMA transfer request Port J2: Input/output port DMA request signal 3: For inputting the request to transfer data by DMA from an external I/O device to DMAC3 Port J3: Input/output port DMA acknowledge signal 3: Signal showing that DREQ3 has acknowledged a DMA transfer request Port K: Input/output port that allows input/output to be set in units of bits KEY on wake up input 0 to 7 (with pull-up) With Schmitt trigger Port L: Input/output port that allows input/output to be set in units of bits Port M: Input/output port that allows input/output to be set in units of bits Port N: Input/output port that allows input/output to be set in units of bits Port O0: Input/output port Interrupt request pin 0: Selectable between "H" level, "L" level, rising edge and falling edge Input pin with Schmitt trigger Port O1: Input/output port Interrupt request pin 1: Selectable between "H" level, "L" level, rising edge and falling edge Input pin with Schmitt trigger Port O2: Input/output port Interrupt request pin 2: Selectable between "H" level, "L" level, rising edge and falling edge Input pin with Schmitt trigger Port O3: Input/output port Interrupt request pin 3: Selectable between "H" level, "L" level, rising edge and falling edge Input pin with Schmitt trigger Port O4: Input/output port Interrupt request pin 4: Selectable between "H" level, "L" level, rising edge and falling edge Input pin with Schmitt trigger Port O5: Input/output port Sending serial data 6: Open drain output pin depending on the program used Port O6: Input/output port Receiving serial data 6 Port O7: Input/output port Serial clock input/output 6 Ready to send serial data 6 (Clear To Send): Open drain output pin depending on the program used Port P: Input/output port that allows input/output to be set in units of bits Outputting trace data from the data access address: Signal for DSU-ICE Port P: Input/output port that allows input/output to be set in units of bits Outputting trace data from the program counter: Signal for DSU-ICE Outputting trace data from the data access address: Signal for DSU-ICE 1 1 1 1 1 8 8 8 8 1 1 1 1 1 1 1 1 8 8 TMP19A64(rev1.1)2-7 TMP19A64C1D Table 2.2.1 Pin Names and Functions (6 of 6) Pin name DCLK EJE PCST4-0 DINT TOVR/TSTA TCK TMS TDI TDO TRST NMI PLLOFF RESET X1/X2 XT1/XT2 BUPMD BRESET BUSMD Number of pins 1 1 5 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 Input or output Output Input Output Input Output Input Input Input Output Input Input Input Input Input/output Input/output Input Input Input Function Debug clock: Signal for DSU-ICE EJTAG enable: Signal for DSU-ICE (input with Schmitt trigger and built-in noise filter) PC trace status: Signal for DSU-ICE Debug interrupt: Signal for DSU-ICE (input with Schmitt trigger, pull-up and built-in noise filter) Outputting the status of PD data overflow status: Signal for DSU-ICE Test clock input: Signal for testing JTAG (input with Schmitt trigger and pull-up) Test mode select input: Signal for testing JTAG (input with Schmitt trigger and pull-up) Test data input: Signal for testing JTAG (input with Schmitt trigger and pull-up) Test data output: Signal for testing JTAG Test reset input: Signal for testing JTAG (input with Schmitt trigger and pull-down) Nonmaskable interrupt request pin: Pin for requesting an interrupt at the falling edge Input with Schmitt trigger and built-in noise filter Fix this pin to the "H (DVCC15) level."(Input with Schmitt trigger) Reset: Initializing LSI (with pull-up) Input with Schmitt trigger and built-in noise filter Pin for connecting to a high-speed oscillator Pin for connecting to a low-speed oscillator Backup mode trigger pin: This pin must be set to "L level" in backup mode. Backup module reset: Initializing the backup module (with pull-up) Input with Schmitt trigger Pin for setting an external bus mode: This pin functions as a multiplexed bus by sampling the "H (DVCC15) level" upon the rising of a reset signal. It also functions as a separate bus by sampling "L" upon the rising of a reset signal. When performing a reset operation, pull it up or down according to a bus mode to be used. Pin for setting endian: This pin is used to set a mode. It performs a big-endian operation by sampling the "H (DVCC15) level" upon the rising of a reset signal, and performs a littleendian operation by sampling "L" upon the rising of a reset signal. When performing a reset operation, pull it up or down according to the type of endian to be used. Pin for setting a single boot mode: This pin goes into single boot mode by sampling "L" upon the rising of a reset signal. It is used to overwrite internal flash memory. By sampling "H (DVCC15) level" upon the rising of a reset signal, it performs a normal operation. This pin should be pulled up under normal operating conditions. Pull it up when resetting. Fix these pins to BW0="H (DVCC15)" and BW1="H (DVCC15)," respectively. (Input with Schmitt trigger) Pin (H) for supplying the A/D converter with a reference power supply Connect this pin to AVCC31 if the A/D converter is not used. Pin (L) for supplying the A/D converter with a reference power supply Connect this pin to AVSS if the A/D converter is not used. Pin for supplying the A/D converter with a power supply. Connect it to a power supply even if the A/D converter is not used. A/D converter GND pin (0 V). Connect this pin to GND even if the A/D converter is not used. TEST pin: To be fixed to GND. Pin for supplying oscillators with power: 1.5 V power supply GND pin (0 V) for oscillators and backup modules Power supply pin: 1.5 V power supply Pin exclusively for supplying backup modules with power: 3 V power supply Power supply pin: 3 V power supply GND pin (0 V) ENDIAN 1 Input BOOT 1 Input BW0-1 VREFH VREFL AVCC31-32 AVSS TEST1-3 CVCC15 CVSS/BVSS DVCC15 BVCC DVCC30-34 DVSS 2 1 1 2 3 3 1 1 4 1 8 11 Input Input Input - - Input - - - - - - TMP19A64(rev1.1)2-8 TMP19A64C1D Note 1: For BUSMD, ENDIAN and BOOT pins, the state designated for each pin ("H" or "L" level) must be maintained during one system clock before and after the rising of a reset signal. The reset pin must always be in a stable state at both "L" and "H" levels. Note 2: For DREQ2, DACK2, DREQ3 and DACK3, it is necessary to go to the port function register and to select one port from two groups of ports, PF3 to PF6 and PJ0 to PJ3. Two ports cannot be operated simultaneously to use the same function. Likewise, for pins INT0 through INT4, one port must be selected from ports PI0 to PI4 and ports PO0 to PO4. Table 2.2.2 shows the pin names and power supply pins. Table 2.2.2 Pin names and power supply pins Pin name P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ Power supply pin DVCC33 DVCC33 DVCC33 DVCC33 DVCC33 DVCC33 DVCC33 AVCC32 AVCC32 AVCC31 DVCC32 DVCC32 DVCC32 DVCC32 DVCC32 DVCC32 DVCC32 DVCC32 DVCC30 DVCC33 DVCC34 DVCC34 DVCC34 DVCC34 DVCC34 DVCC31 DVCC31 Pin name PCST4 to 0 DCLK EJE TRST TDI TDO TMS TCK DINT TOV BUSMD BOOT ENDIAN NMI BRESET BUPMD X1, X2 XT1, XT2 BW0 and 1 PLLOFF RESET Power supply pin DVCC31 DVCC31 DVCC31 DVCC31 DVCC31 DVCC31 DVCC31 DVCC31 DVCC31 DVCC31 DVCC15 DVCC15 DVCC15 DVCC15 BVCC BVCC CVCC15 BVCC DVCC15 DVCC15 DVCC15 2.7 V AVCC32 AVCC31 TMP19A64(rev1.1)2-9 TMP19A64C1D Table 2.2.3 shows the pin numbers and power supply pins. Table 2.2.3 Pin numbers and power supply pins Power supply pin DVCC15 CVCC15 DVCC30 DVCC31 DVCC32 DVCC33 DVCC34 AVCC31 AVCC32 BVCC Pin number D4, D8, E18, N9 C17 K17 H2 M6, U8 F17, U14 D15, F10 B1 F9 E15 Voltage range 1.35 V to 1.65 V 1.35 V to 1.65 V 1.65 V to 3.3 V 1.65 V to 3.3 V 1.65 V to 3.3 V 1.65 V to 3.3 V 1.65 V to 3.3 V 2.7 V to 3.3 V 2.7 V to 3.3 V 2.3 V to 3.3 V (under normal operating conditions) 1.8 V to 3.3 V (in BACKUP mode) TMP19A64(rev1.1)2-10 TMP19A64C1D 3. Processor Core The TMP19A64 has a high-performance 32-bit processor core (TX19A processor core). For information on the operations of this processor core, please refer to the "TX19A Family Architecture." This chapter describes the functions unique to the TMP19A64 that are not explained in that document. 3.1 Reset Operation To reset the device, ensure that the power supply voltage is in the operating voltage range, the oscillation of the internal high-frequency oscillator has stabilized at the specified frequency and that the RESET input has been "0" for at least 12 system clocks (1.78 s during external 13.5 MHz operation). Note that the PLL multiplication clock is quadrupled and the clock gear is initialized to the 1/8 mode during the reset period. When the reset request is authorized, * * the system control coprocessor (CP0) register of the TX19A processor core is initialized. For further details, please refer to the chapter about architecture. After the reset exception handling is executed, the program branches off to the exception handler. The address to which the program branches off to (address where exception handling starts) is called an exception vector address. This exception vector address of a reset exception (for example, nonmaskable interrupt) is 0xBFC0_0000H (virtual address). The register of the internal I/O is initialized. The port pin (including the pin that can also be used by the internal I/O) is set to a general-purpose input or output port mode. * * (Note 1) Set the RESET pin to "0" before turning the power on. Perform the reset after the power supply voltage has stabilized sufficiently within the operating range. (Note 2) The reset operation can alter the internal RAM state, but does not alter data in the backup RAM. (Note 3) Make sure that the power supply voltage has stabilized, wait for 500 s or longer, and perform the reset. (Note 4) In the FLASH program, the reset period of 0.5 uS or longer is required independently of the system clock. TMP19A64 (rev1.1) 3-1 TMP19A64C1D 4. Memory Map Fig. 4.1 shows the memory map of the TMP19A64. Virtual address 0xFFFF FFFF 0xFF00 0000 16 MB reserved Kseg2 (1 GB) Physical address 16 MB reserved Kseg2 (cash enabled) 16 MB reserved Internal RAM (64 KB) Internal I/O 0xFFFF E000 Internal RAM area 0xFFFF DFFF (56 KB) projection 0xFFFF 0000 (reserved) 0xFFFD FFFF 0xFFFD 0000 0xFF3F FFFF 0xFF20 0000 0XBFCF FFFF 0xBFC0 0000 0xA000 0000 0x8000 0000 Kseg1 (cash disabled) Kuseg (2 GB) 16 MB reserved (reserved) Kseg0 (cash enabled) Reserved for debugging (2 MB) (reserved) Internal ROM area 0x401F FFFF projection 0x4000 0000 Inaccessible Internal ROM 0x1FDF FFFF 0x1FC0 0000 0xFF00 0000 0x1FDF FFFF User program area Kuseg (cash enabled) 0x000F FFFF 0x0000 0000 512 MB Maskable interrupt area Exception vector area 0x1FC0 0400 0x1FC0 0000 Fig. 4.1 Memory Map (Note 1) The internal ROM is physically present in 0x1FC0_0000-0x1FDF_FFFF (2 MB). The internal RAM is physically present in 0xFFFD_0000-0xFFFD_FFFF (64 KB). 0xFFFF_0000-0xFFFF_DFFF (56 KB) becomes the projection area. You can access the internal RAM by accessing this area. The internal backup RAM area becomes 0xFFFF_E800-0xFFFF_E9FF (512 B). (Note 2) For the TMP19A64, a physical space of only 16 MB is available as external address space to be accessed. It is possible to place this 16-MB physical address space in a chip select area of your choice inside the 3.5-GB physical address space of the CPU. Access to internal memory, internal I/O space and reserved areas is given priority over access to the external address space. Therefore, access to the external address space is denied if any of the internal memory, internal I/O space or reserved areas are being accessed. (Note 3) Do not place an instruction in the last four words of a physical area, specifically the last four words of an area where memory is mounted for external ROM extension (this varies depending on the system of the user). Internal ROM: 0x1FDF_FFF0-0x1FDF_FFFF TMP19A64 (rev1.1) 4-1 TMP19A64C1D 5. Clock/Standby Control 5.1 System Operation Modes The system operation modes contain the standby modes in which the processor core operations are stopped to reduce power consumption. Fig. 5.1.1 State Transition Diagram of Each Operation Mode is shown below. Reset Reset has been performed IDLE mode (CPU stop) (I/O selective operation) Instruction Interrupt NORMAL mode (fc/gear value) Instruction Interrupt STOP mode (Entire circuit stop) State Transition Diagram of Clock Mode When No Power is Supplied to the Backup Module Reset Main power on Reset has been performed IDLE mode (CPU stop) (I/O selective operation) Instruction Interrupt Interrupt NORMAL mode (fc/gear value) Instruction Instruction Instruction SLEEP mode (fs only) Instruction Interrupt Interrupt Instruction STOP mode (Note 1) Interrupt External input & main power off (Note 2) SLOW mode (fs) BACKUP mode (fs only) External input & main power off (Note 2) State Transition Diagram of Clock Mode When Power is Supplied to the Backup Module (Note 1) STOP mode: All the circuits except the backup module are brought to a stop. The backup module continues operation (fs continues oscillation). (Note 2) External input: It is necessary to activate the BUPMD pin during the RESET period. For details, see the chapter on Backup RAM. Fig. 5.1.1 State Transition Diagram of Each Operation Mode TMP19A64 (rev1.1) 5-1 TMP19A64C1D 5.2 Default State of the System Clock Reset Reset has been performed PLLOFF pin ("H") Use the PLL clock NORMAL mode fc = fpll = foscx4 fsys = fc/8 fsys = fosc/2 fperiph =fgear= fsys Fig. 5.2.1 Initial State of the System Clock fosc: fpll: fc: fs: fgear: fsys: High-frequency clock frequency to be input via the X1 and X2 pins Clock frequency multiplied (quadrupled) by the PLL Clock frequency when the PLLOFF pin is in the "H" state Low-frequency clock frequency to be input via the XT1 and XT2 pins Clock frequency selected by the system control register SYSCR1 fperiph: Clock frequency selected by SYSCR1 TMP19A64 (rev1.1) 5-2 TMP19A64C1D 5.3 Clock System Block Diagram 5.3.1 Main System Clock * * * * Allows for oscillator connection or external clock input. Keep the PLLOFF pin (PLL (quadruple)) at the "H" level. Clock gear (8/8, 7/8, 6/8, 5/8, 4/8, 2/8, 1/8) (Default is 1/8.) Input frequency (high frequency) Input frequency range PLL operation (for both oscillators and external input) 8-13.5 (MHz) Maximum operating frequency 54 MHz Lowest operating frequency 4 MHz * * Clock gear 1/8 (default) is used when 8 MHz (MIN) is input. * Input frequency (low frequency) Input frequency range 30 KHz to 34 KHz Maximum operating frequency 34 KHz Lowest operating frequency 30 KHz (Note) (precautions for switching the high-speed clock gear) Switching of clock gear is executed when a value is written to the SYSCR1 TMP19A64 (rev1.1) 5-3 TMP19A64C1D 5.3.2 Clock Gear * * The high-speed clock is divided into 8/8, 7/8, 6/8, 5/8, 4/8, 2/8 or 1/8. The internal I/O prescaler clock T0: fperiph/2, fperiph/4, fperiph/8 and fperiph/16 Fig. 5.3.1 shows the system clock transition diagram. SYSCR0 Warm-up timer fc (fs) /2 fgear fsys SYSCR1 1/2 1/4 1/8 SYSCR1 High-speed oscillator fosc fpll = fosc x 4 SYSCR1 fsys SYSCR0 CPU ROM RAM DMAC fperiph /2 /4 /8 /16 INTC ADC,TMRB/C, /2 XT1 XT2 (fs) Clock timer T0 Input to peripheral I/O prescaler TMRB/C, SIO, SBI, SIO, SBI, WDT, Port Peripheral I/O Low-speed oscillator fs 2-phase pulse input counter SYSCR3 SCOUT T0 Fig. 5.3.1 System Clock Transition Diagram TMP19A64 (rev1.1) 5-4 TMP19A64C1D 5.4 CG Registers 5.4.1 System Control Registers 7 XEN R/W 1 High-speed oscillator 0: Stop 1: Oscillation 6 R/W 1 Write "1." SYSCR0 (0xFFFF_EE00) bit Symbol Read/Write After reset Function 5 RXEN R/W 1 High-speed oscillator after the STOP mode is released 0: Stop 1: Oscillation 4 R/W 1 Write "1." 3 R 0 This can be read as "0." 2 WUEF R/W 0 Control of warm-up timer (WUP) for oscillator 0 write: don't care 1 write: WUP Start 1 0 PRCK1 PRCK0 R/W R/W 0 0 Select prescaler clock 00: fperiph/16 01: fperiph/8 10: fperiph/4 11: fperiph/2 15 SYSCR1 (0xFFFF_EE01) Bitsymbol Read/Write After reset Function R 0 This can be read as "0." SYSCR2 (0xFFFF_EE02) Bitsymbol Read/Write After reset Function 23 DRVOSCH R/W 0 High-speed oscillator current control 0: High capability 1: Low capability 14 SYSCKFLG R 0 System clock status flag 0: High speed (fc) 1: Low speed (fs) 22 R/W 0 Write 0. 13 SYSCK R/W 0 Select system clock 0: High speed (fc) 1: Low speed (fs) 12 FPSEL R/W 0 Select fperiph 0: fgear 1: fc 11 SGEAR R/W 0 Select gear of low-speed clock 0: fs/1 1:fs/2 0 read: WUP finished 1 read: WUP operating 10 9 8 GEAR2 GEAR1 GEAR0 R/W R/W R/W 1 1 1 Select gear of high-speed clock (fc) 000: fc 100: fc4/8 001: fc7/8 101: reserved 010: fc6/8 110: fc2/8 011: fc5/8 111: fc1/8 21 20 WUPT1 WUPT0 R/W R/W 1 0 Select oscillator warm-up time 00: No WUP 01: 2 /Input frequency 10: 214 /Input frequency 11: 216 /Input frequency 28 ALESEL R/W 1 Set ALE output width 0:fsysx1 1:fsysx2 19 18 STBY1 STBY0 R/W R/W 1 1 Select standby mode 00:Reserved 01:STOP 10:SLEEP 11:IDLE 17 R 0 This can be read as "0." 16 DRVE R/W 0 1: Drive the pin even in the STOP mode. 31 SYSCR3 (0xFFFF_EE03) Bitsymbol Read/Write After reset Function R 0 This can be read as "0." 30 29 SCOSEL1 SCOSEL0 R/W R/W 0 1 Select SCOUT output 00:fs 01:fperiph 10:fsys 11:T0 27 26 25 24 0 R 0 0 This can be read as "0." 0 * * * Don't switch the SYSCK and the GEAR<2:0> simultaneously. If the system enters the STOP mode with SYSCR2 (Note) Restriction on use of the clock gear When using the clock gear to operate the peripheral I/O, set the SYSCR1 TMP19A64 (rev1.1) 5-5 TMP19A64C1D 5.5 System Clock Controller By resetting the system clock controller, the controller status is initialized to (Note) Set the initial system clock frequency to 4 MHz or higher. 5.5.1 Oscillation Stabilization Time (Switching between the NORMAL and SLOW modes) The warm-up timer is provided to confirm the oscillation stability of the oscillator when it is connected to the oscillator connection pin. The warm-up time can be selected by setting the SYSCR2 (Note 1) Warm-up is not required when an oscillator is used for the clock and providing stable oscillation. (Note 2) The warm-up timer operates according to the oscillation clock, and it can contain errors if there is any fluctuation in the oscillation frequency. Therefore, the warm-up time should be taken as approximate time. Table 5.5.1 Warm-up Time Warm-up time options SYSCR2 14 High-speed clock (fosc) 18.963 (s) 1.214 (ms) 4.855 (ms) These values are calculated under the following condition: fosc = 13.5 MHz TMP19A64 (rev1.1) 5-6 TMP19A64C1D SYSCR1 (Note) In the SLOW mode, the CPU operates with the low-speed clock, and the INTC, the backup block, the 2-phase pulse input counter, the KWUP, the IO port and the EBIF (external bus interface) are operable. Stop other internal peripheral functions before the system enters the SLOW mode. 5.5.2 System Clock Pin Output Function The system clock, fsys, fsys/2 or fs, can be output from the P46/SCOUT pin. By setting the port 4 related registers, P4CR Table 5.5.2 SCOUT Output State in Each Standby Mode Mode SCOUT selection NORMAL SLOW Standby mode IDLE SLEEP STOP Output the fs clock. Output the fpriph clock. Output the fsys clock. Output the Fixed to "0." T0 clock. Fixed to "0" or "1." Fixed to "0." (Note) The phase difference (AC timing) between the system clock output by the SCOUT and the internal clock is not guaranteed. TMP19A64 (rev1.1) 5-7 TMP19A64C1D 5.5.3 Reducing the Oscillator Driving Capability This function is intended for restricting oscillation noise generated from the oscillator and reducing the power consumption of the oscillator when it is connected to the oscillator connection pin. Setting the SYSCR2 fOSC C1 Oscillator C2 X2 pin X1 pin Enable oscillation SYSCR2 Fig. 5.5.1 Oscillator Driving Capability 5.5.4 Clock Frequency Division for Low-Speed System Clock The low-speed clock (fs) can be divided into two by setting the system control register SYSCR1 TMP19A64 (rev1.1) 5-8 TMP19A64C1D 5.6 Prescaler Clock Controller Each internal I/O (TMRB0-A, TMRC, SIO0-6 and SBI) has a prescaler for dividing a clock. The clock T0 to be input to each prescaler is obtained by selecting the "fperiph" clock at the SYSCR1 5.7 Clock Multiplication Circuit (PLL) Keep the PLLOFF pin at the "H" level. This pin is the circuit that outputs the fpll clock that is a quadruple of the output clock of the high-speed oscillator, fosc. This lowers the oscillator input frequency while increasing the internal clock speed. 5.8 Flash Access Control Circuit (PFB) The PFBWAIT register can be used to select the speed of access to the flash memory. You need to set an appropriate flash access speed for the operating frequency to be used. 31 - 2 PFBWAIT (0xFFFF_E500) bit Symbol Read/Write After reset R 0 1 PFBWAIT R/W 1 0 R/W 1 PFBWAIT: WAIT number 11: 4-clock access/10: 3-clock access/01: 2-clock access 00: Setting disabled Operating frequency (fc) MHz PFBWAIT<1:0> 11 10 01 00 - x - x - 40< 45 <=54 : Settable x: Not settable -: Setting prohibited Note) If an appropriate access speed is not specified, the program can operate improperly. TMP19A64 (rev1.1) 5-9 TMP19A64C1D 5.9 Standby Controller The TX19A core has several low-consumption modes. To shift to the STOP, SLEEP or IDLE (Halt or Doze) mode, set the RP bit in the CPO status register, and then execute the WAIT instruction. Before shifting to the mode, you need to select the standby mode at the system control register (SYSCR2). The IDLE, SLEEP and STOP modes have the following features: IDLE: Only the CPU is stopped in this mode. The internal I/O has one bit of the ON/OFF setting register for operation in the IDLE mode in the register of each module. This enables operation settings for the IDLE mode. When the internal I/O has been set not to operate in the IDLE mode, it stops operation and holds the state when the system enters the IDLE mode. Table 5.9.1 shows a list of IDLE setting registers. Table 5.9.1 Internal I/O Setting Registers for the IDLE Mode Internal I/O TMRB0-A TBT SIO0-6 SBI A/D converter WDT IDLE mode setting register TBxRUN (Note 1) The Halt mode is activated by setting the RP bit in the status register to "0," executing the WAIT command and shifting to the standby mode. In this mode, the TX19A processor core stops the processer operation while holding the status of the pipeline. The TX19A gives no response to the bus control authority request from the internal DMA, so the bus control authority is maintained in this mode. (Note 2) The Doze mode is activated by setting the RP bit in the status register to "1" and shifting to the standby mode. In this mode, the TX19A processor core stops the processer operation while holding the status of the pipeline. The TX19A can respond to the bus control authority request given from the outside of the processor core. SLEEP: Only the internal low-speed oscillator, the backup block, the 2-phase pulse input counter operate. STOP: All the internal circuits are brought to a stop. TMP19A64 (rev1.1) 5-10 TMP19A64C1D 5.9.1 CG Operations in Each Mode Table5.9.1 Status of CG in Each Operation Mode Clock source Oscillator Mode Normal Slow Idle (Halt) Idle (Doze) Sleep Stop fs only x : ON or clock supply x x Oscillation circuit PLL x Clock supply to peripheral I/O Partial supply (Note) Selectable Selectable Backup block/2-phase pulse input counter x x: OFF or no clock supply x x x x Clock supply to CPU (Note) Peripheral functions that can work in the SLOW mode: INTC, external bus interface, IO port, backup block and 2-phase pulse input counter 5.9.2 Block Operations in Each Mode Table 5.9.2 Block Operating Status in Each Operation Mode Block NORMAL SLOW IDLE (Doze) x IDLE (Halt) x x x x x x x x x x (Note 1) x (Note 2) x x x SLEEP x x x x x x x x x x x STOP x x x x x x x x x x x x /x (Note 3) BACKUP x x x x x x x x x x x x TX19A processor core DMAC INTC External bus I/F IO port ADC SIO I2C TMRB TMRC WDT 2-phase counter Backup block KWUP CG High-speed oscillator (fc) Low-speed oscillator (fs) : ON x: OFF ON/OFF selectable for each module x x x * Low-speed oscillation is active when the BVCC is applied, and not active when the BVCC is shut off. (Note 1) The backup RAM is inaccessible in the SLOW mode. (Note 2) When the system enters the SLOW mode, the high-speed oscillator must be stopped by setting the SYSCR1 BUPMD pin. TMP19A64 (rev1.1) 5-11 TMP19A64C1D 5.9.3 Releasing the Standby State The standby state can be released by an interrupt request when the interrupt level is higher than the interrupt mask level, or by the reset. The standby release source that can be used is determined by a combination of the standby mode and the state of the interrupt mask register TMP19A64 (rev1.1) 5-12 TMP19A64C1D Table 5.9.3 Standby Release Sources and Standby Release Operations (Interrupt level)>(Interrupt mask) Interrupt accepting state Standby mode INTWDT INT0-B Standby release source (Note 1) KWUP0-7 Interrupt (Note 1) INTRTC INTTBA (Note 2) INTTB0-9 INTRX0-6, TX0-6 INTS INTAD/ADHP/ADM x x x x x x x x x x x x x Interrupt enabled EI= "1" IDLE SLEEP STOP (programmable) x x Interrupt disabled EI= "0" IDLE SLEEP STOP (programmable) - - (Note 1) (Note 1) x x x x x x - : Starts the interrupt handling after the standby mode is released. (The LSI is initialized by the reset.) : Starts the processing at the address next to the standby instruction (without executing the interrupt handling) after the standby mode is released. : Cannot be used for releasing the standby mode : Cannot execute masking with an interruption mask when a nonmaskable interrupt is selected. (Note 1) The standby mode is released after the warm-up time has elapsed. (Note 2) These operations are applicable only when the 2-phase pulse input counter mode is selected. If any other modes are selected, the operations will be the same as those for the INTTB0 to INTTB9. To release the standby mode by using the level mode interrupt in the interruptible state, keep the level until the interrupt handling is started. Changing the level before then will prevent the interrupt processing from starting properly. To enter the standby mode when the CPU has disabled the acceptance of interrupts, disable interrupts other than the recovery factors in advance by using the interrupt controller (INTC). Otherwise, the standby mode can be released by any other interrupts than the recovery factors. To recover from the standby mode when the CPU has disabled the acceptance of interrupts, set the interrupt level higher than the interrupt mask (Interrupt level > Interrupt mask). If the interrupt level is equal to or lower than the interrupt mask (Interrupt level Interrupt mask), the system cannot recover from the standby mode. TMP19A64 (rev1.1) 5-13 TMP19A64C1D 5.9.4 STOP Mode In the STOP mode, all the internal circuits, including the internal oscillators, are brought to a stop. The pin states in the STOP mode vary depending on the setting of the SYSCR2 (Note) To shift from the NORMAL mode to the STOP mode on the TMP19A64, do not set the SYSCR2 Table 5.9.4 Warm-up Settings for Transitions of Operation Modes Transition of operation mode NORMAL IDLE NORMAL SLEEP NORMAL SLOW NORMAL STOP IDLE NORMAL SLEEP NORMAL SLEEP SLOW SLOW NORMAL SLOW SLEEP SLOW STOP STOP NORMAL STOP SLOW Warm-up setting Not required Not required Not required Not required Not required Required Not required Required (Note 1) Not required Not required Required Not required Note 1) When the high-speed oscillator is stopped in the SLOW mode TMP19A64 (rev1.1) 5-14 TMP19A64C1D (NOTE)19A64 requires a recovery time from Warming up state as following RESET Reset Release IDLE Mode (CPU Stop) (Selective I/O ) Software Interrupt Softwar NORMAL Mode (fc/ gear) A Software F SLEEP Mode (fs) C Interrupt Softwar G Interrupt E STOP Mode SLOW Mode (fs) Soft B Interrupt Softwar D Interrupt H All Stoped WUP Trigger State Transition Diagram State Running Mode after WUP Minimum required Operation time Transition before WAIT instruction done (sec) STOP release A B C D STOP/SLEEP STOP/SLEEP STOP/SLEEP STOP/SLEEP 64 / fsys in NOMAL mode 16 / fsys in SLOW mode 64 / fsys in NOMAL mode - SLEEP release TMP19A64 (rev1.1) 5-15 TMP19A64C1D 5.9.5 1. Recovery from the STOP or SLEEP Mode Transition of operation modes: NORMAL STOP NORMAL System clock off fsys (High-speed clock) mode CG (High-speed clock) Start of high-speed clock oscillation Warm-up (W-up) Start of warm-up End of warm-up NORMAL STOP NORMAL when @fosc=13.5 MHz Selection of warm-up time SYSCR2 (Note) When @fosc=13.5 MHz, the internal system recovery time cannot be satisfied. Do not set 2. Transition of operation modes: NORMAL SLEEP NORMAL System clock off fsys (High-speed clock) mode NORMAL SLEEP NORMAL CG (High-speed clock) CG (Low-speed clock) Low-speed clock (fs) continues oscillation Warm-up (W-up) Start of high-speed clock oscillation Start of warm-up End of warm-up when @fosc=13.5 MHz Selection of warm-up time SYSCR2 (Note) When @fosc=13.5 MHz, the internal system recovery time cannot be satisfied. Do not set TMP19A64 (rev1.1) 5-16 TMP19A64C1D 3. Transition of operation modes: SLOW STOP SLOW fsys (Low-speed clock) mode System clock off SLOW STOP SLOW CG (fs) (Low-speed clock) (Note) The low-speed clock (fs) continues oscillation. There is no need to make a warm-up setting. 4. Transition of operation modes: SLOW SLEEP SLOW fsys (Low-speed clock) mode System clock off SLOW STOP SLOW CG (fs) (Low-speed clock) (Note) The low-speed clock (fs) continues oscillation. There is no need to make a warm-up setting. TMP19A64 (rev1.1) 5-17 TMP19A64C1D Table 5.9.6 Pin States in the STOP Mode in Each State of SYSCR2 Pin name P00-P07 Input/output Input mode Output mode AD0-AD7, D0-D7 Input mode Output mode, A8-A15 AD8-AD15, D8-D15 Input mode Output mode, A0-A7/A16-A23 Output pin Input mode Output mode, /HWR, /BUSAK, R/W_ Input mode, /WAIT, /RDY Output mode Input mode Output mode BUSRQ Input mode Output mode ALE (Output mode) Input mode Output mode, CS0-CS5 Input mode Output mode Input mode Output mode Input mode Output mode, A0-A7 Input mode Output mode, A8-A15 Input pin, AN0-AN23 Input mode Output mode INT5-INT8 (Input mode) Input mode Output mode, TB0OUT,TB1-3OUT Input mode, TBAIN1 Output mode, TB4-9OUT Input mode, SCLK0-1, RXD0-2, /CTS0-1 Output mode, SCLK0-1,TXD0-2 Input mode, SCLK2-4, RXD3-4, /CTS2-4 Output mode, SCLK2-4,TXD3-4 Input mode Output mode INT9 (Input mode) Input mode, SCLK5, RXD5, /CTS5 Output mode, SCLK5, TXD5 Input mode Output mode Input mode Output mode INTA-INTB (Input mode) P10-P17 P20-P27 P30 (/RD), P31 (/WR) P32, P35, P36 P33 P34 P37 (ALE) P40-P45 P46 (SCOUT) P47 P50-P57 P60-P67 P7, P8, P9 PA0, PA1, PA3, PA4 cPA2, PA5, PA6, PA7 PB0-PB7 PC0-PC7 PD0-PD6 PD7 PE0-PE2 PE3-PE5 PE6-PE7 TMP19A64 (rev1.1) 5-18 TMP19A64C1D Table 5.9.6 Pin States in the STOP Mode in Each State of SYSCR2 Pin name PF0-PF7 Input/Output Input mode, SDA, SI, SCL, SCK, /DREQ2-, TBTIN Output mode, SO, SDA, SCL, SCK, /DACK2-3 Input mode, TC0-3IN Output mode, TCOUT0-3 Input mode Output mode, TCOUT4-9 Input mode Output mode Input mode Output mode INT0-INT4 (Input mode) Input mode, /DREQ2-3 Output mode, /DACK2-3 Input mode Output mode KEY0-KEY7 (Input mode) Input mode Output mode Input mode Output mode INT0-INT4 (Input mode) Input mode, RXD6, /CTS6 Output mode, TXD6, Input mode Output mode TPD0-7, TPC0-7 Input pin Input pin Input pin Input pin Input pin Input pin Input pin Input pin Input pin Input pin Input pin Output pin PG0-PG7 PH0-PH5 PH6-PH7 PI0-PI4 PJ0-PJ3 PK0-PK7 PL, PM, PN PO0-PO4 PO5-PO7 PP, PQ NMI PLLOFF RESET BUPMD BRESET BUSMD ENDIAN BOOT BW0-1 TEST1-3 X1 X2 : Indicates that the input is disabled for the input mode and the input pin and the impedance becomes high for the output mode and the output pin. Note that the input is enabled when the port function register (PxFC) is "1" and the port control register (PxCR) is "0." : The input gate is active. To prevent the input pin from floating, fix the input voltage to the "L" or "H" level. : This is the programmable pull-up pin. The input gate is always disabled. No feedthrough current flows even if the high impedance is selected. Input Output : The pin is in the output state. PU* TMP19A64 (rev1.1) 5-19 TMP19A64C1D 6. 6.1 Interrupts Overview The features of the TX19A64 interrupts are as follows: * * * * * * 2 interrupts from the CPU itself (software interrupt instruction) 21 external pins ( NMI , INT0 to INTB, KWUP0 to 7) 51 interrupts from internal I/O (including WDT interrupt) Generation of vectors for each interrupt factor Seven interrupt levels for each interrupt factor An interrupt can be used to activate the DMAC. (1) Preparation for interrupt settings * Settings required before generating interrupts: Set the exception table base address (the base address of the table of maskable interrupt jump addresses) to IVR. Set the interrupt jump addresses to the "exception table base address + IVR offset address" memory. Set Status TMP19A64(rev1.1) 6-1 TMP19A64C1D CG Detection circuit 3 NMI WDT Write Bus Error Active H level 15 Rising edge 15 Rising edge H level Status register 15 1 1 1 INTTBA TMRB H/L level or edge setting 12 INTC INT0 to B IMCxx register Core RTC 15 INTnEN Standby clear control IMCGxx register Other interrupts KWUP H/L level or edge setting Input enable/disable for each interrupt factor KWUP0 to 7 register KWUP KWUP0 to 7 Fig. 6.1.1 Interrupt Connection Diagram TMP19A64(rev1.1) 6-2 TMP19A64C1D (2) Interrupts from external pins (INT0 - INTB and KWUP0-7) When any external interrupt is to be used for setting to clear the Standby mode, use the following steps: Set ports Set functions Set CG Clear the EICRCG and INTCLR registers of CG Enable interrupts with INT a) INT0 - INTB If it is used to clear the Stop mode: IMCGx EICRCG INTCLR INTCLR = "01" : Set each interrupt request (INT0-B) to the H level (Refer to INTC register). : Set the KWUP standby clear request to "active" (Refer to INTCG register). : Set the KWUP clear input to "enable" (Refer to INTCG register). : Set KWUP interrupt request to the H level (Refer to INTC register). : Clear KWUP interrupt request (Refer to INTCG register). (Refer to INTCG register). = "01" = "01" = "000110100" : Clear KWUP interrupt request KWUPST : Set each KWUP interrupt factor to Enable (Refer to KWUP register). Table 6.1.2 Registers to be Set for Detecting Interrupts Interrupt INT0 - INTB,KWUP Interrupt detection levels that can be used When in use, set to a rising edge in INTC (if edge detection is set for CG) or to "H" level (if level detection is set for CG). Set the active state in CG. The "L" level, "H" level, falling edge, or rising edge setting can be selected in CG register. Internal I/O (Note 1) Others Falling edge Interrupt level 0 means that the interrupt is disabled. TMP19A64(rev1.1) 6-3 TMP19A64C1D (3) Interrupt operation Basic interrupt handling In the interrupt handler (Refer to Table 6.2.1 Interrupt Jump Address for the starting address of the interrupt handler): * * * Read the IVR value (in the figure, IVR value is 0x8000) Substitute the IVR value for ICLR to clear the interrupt factor. Obtain the exception handling jump address by using the IVR value (in the figure, it is 0x8000) as the corresponding address in the table (in the figure, the "jump to" address is 0x9000). Jump to the exception handling routine using the "jump to" address. * In the interrupt processing routine: * * * Execute the interrupt processing Set ILEV Note that interrupts are disabled during the exception handling except for the case multiple interrupts are allowed. memory IVR 0x8000 0x8000 0x9000 0x9000 Exception handler Fig. 6.1.3 Process Flow in the Interrupt Handler TMP19A64(rev1.1) 6-4 TMP19A64C1D 6.2 Interrupt Factor The starting address of an exception handler is defined as "exception vector address." The exception vector address for a reset exception and non-maskable interrupts is 0xBFC0_0000. The exception vector address for a debug exception is 0xBFC0_0480 (EJTAG ProbEn = 0). For other exceptions, the corresponding exception vector addresses are determined depending on the BEV bit of Status register [23] and the IV bit of the Cause register [23] of the system control coprocessor register (CP0). Table 6.2.1 Interrupt Branch Address BEV=0 Exception Reset EJTAG Debug (En=0) EJTAG Debug (En=1) Interrupt (IV=0) Interrupt (IV=1) All others Virtual address 0xBFC0_0000 0xBFC0_0480 0xFF20_0200 0x8000_0180 0x8000_0200 0x8000_0180 Logical address 0x1FC0_0000 0x1FC0_0480 0xFF20_0200 0x0000_0180 0x0000_0200 0x0000_0180 0xBFC0_0000 0xBFC0_0480 0xFF20_0200 0xBFC0_0380 0xBFC0_0400 0xBFC0_0380 BEV=1 Virtual address Logical address 0x1FC0_0000 0x1FC0_0480 0xFF20_0200 0x1FC0_0380 0x1FC0_0400 0x1FC0_0380 (Note 1) (Note 2) If vector addresses are to be placed in the internal ROM, set the status bit TMP19A64(rev1.1) 6-5 TMP19A64C1D Table 6.2.2 List of Hardware Interrupt Factors Interrupt Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 IVR[8:0] 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C 0x050 0x054 0x058 0x05C 0x060 0x064 0x068 0x06C 0x070 0x074 0x078 0x07C 0x080 0x084 0x088 0x08C 0x090 0x094 0x098 0x09C 0x0A0 0x0A4 0x0A8 0x0AC 0x0B0 0x0B4 0x0B8 0x0BC 0x0C0 0x0C4 0x0C8 0x0CC 0x0D0 0x0D4 0x0D8 0x0DC 0x0E0 0x0E4 0x0E8 0x0EC 0x0F0 0x0F4 0x0F8 0x0FC Software set INT0 pin INT1 pin INT2 pin INT3 pin INT4 pin INT5 pin INT6 pin INT7 pin INT8 pin INT9 pin INTA pin INTB pin KWUP INTRX0 INTTX0 INTRX1 INTTX1 INTRX2 INTTX2 INTSBI INTADHP INTADM INTTB0 INTTB1 INTTB2 INTTB3 INTTB4 INTCAPG INTCMP0 INTCMP1 INTCMP2 INTCMP3 INTCMP4 reserved INTRX3 INTTX3 INTRX4 INTTX4 INTRX5 INTTX5 INTRX6 INTTX6 INTTB5 INTTB6 INTTB7 INTTB8 INTTB9 INTTBA INTCMP5 INTCMP6 INTCMP7 INTCMP8 INTCMP9 INTRTC INTAD INTDMA0 INTDMA1 INTDMA2 INTDMA3 INTDMA4 INTDMA5 INTDMA6 INTDMA7 Interrupt Factor Interrupt Control Register IMC0 Address 0xFFFF_E000 IMC1 0xFFFF_E004 IMC2 0xFFFF_E008 IMC3 : Serial receiving (channel.0) : Serial transmit (channel.0) : Serial receiving (channel.1) : Serial transmit (channel.1) : Serial receiving (channel.2) : Serial transmit (channel.2) : Serial bus interface 0 : Highest priority ADC complete interrupt : ADC monitor function interrupt : 16-bit timer 0 : 16-bit timer 1 : 16-bit timer 2 : 16-bit timer 3 : 16-bit timer 4 : Input capture group : Compare interrupt 0 : Compare interrupt 1 : Compare interrupt 2 : Compare interrupt 3 : Compare interrupt 4 : Serial receiving (channel.3) : Serial transmit (channel.3) : Serial receiving (channel.4) : Serial transmit (channel.4) : Serial receiving (channel.5) : Serial transmit (channel.5) : Serial receiving (channel.6) : Serial transmit (channel.6) : 16-bit timer 5 : 16-bit timer 6 : 16-bit timer 7 : 16-bit timer 8 : 16-bit timer 9 : 16-bit timer A : Compare interrupt 5 : Compare interrupt 6 : Compare interrupt 7 : Compare interrupt 8 : Compare interrupt 9 : Clock timer : ADC completed : Completion of DMA transfer : Completion of DMA transfer : Completion of DMA transfer : Completion of DMA transfer : Completion of DMA transfer : Completion of DMA transfer : Completion of DMA transfer : Completion of DMA transfer 0xFFFF_E00C IMC4 0xFFFF_E010 IMC5 0xFFFF_E014 IMC6 0xFFFF_E018 IMC7 0xFFFF_E01C IMC8 0xFFFF_E020 IMC9 0xFFFF_E024 IMCA 0xFFFF_E028 IMCB 0xFFFF_E02C IMCC 0xFFFF_E030 IMCD 0xFFFF_E034 (channel.0) (channel.1) (channel.2) (channel.3) (channel.4) (channel.5) (channel.6) (channel.7) IMCE 0xFFFF_E038 IMCF 0xFFFF_E03C TMP19A64(rev1.1) 6-6 TMP19A64C1D Table 6.2.3 Interrupt Factors to Cancel Stop/Sleep/Idle Modes Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Interrupt Factor INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT8 INT9 INTA INTB KWUP INTRTC INTTBA reserved Note External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 External interrupt 8 External interrupt 9 External interrupt A External interrupt B Key on wake up interrupt Clock timer interrupt Two-phase pulse input counter interrupt * Number 0 to 13 interrupt factors can cancel Stop/Sleep modes. * Number 14 interrupt factor can cancel the Sleep mode. * Each factor can clear the IDLE mode. TMP19A64(rev1.1) 6-7 TMP19A64C1D 6.3 Interrupt Detection If any interrupt is used to cancel the Stop mode, interrupt active states of INT0 to INTB must be set in the EMCGxx field of the IMCGx register in CG and the EIMxx of the IMCx register in INTC must be set to "H" level. For KWUP0 to 7, the EMCG field of the IMCGD register in CG must be set to "H" and the EIMxx field of the IMCx register in INTC must be set to "H" level. The active state as well as enable/disable is set in KWUPSTn for each interrupt. For setting other interrupts, the EIMxx field of the IMCx register in INTC is used. Four types of active states, "H" level, "L" level, rising edge, and falling edge, are used. When the interrupt detection circuit of TMP19A64 recognizes that any input state matches with the predefined active state, it notifies the processor core or INTC of an interrupt request. If the interrupts that can be used to cancel the Stop mode are not to be used for canceling Stop mode, it is unnecessary to configure them in CG. In this case, INT0 to INTB can be set only by INTC and KWUP0 to 7 can be set in INTC and KWUPSTx. The interrupt signal is negated by the interrupt handler after the interrupt factor is identified. In the case of INT0 to INTB, appropriate values are written to the ICRCG field of the EICRCG register and to the EICLR field of the INTCLR register in INTC. KWUP0 to 7 are negated by setting KWUPCLR. Other interrupt signals are negated by writing a given value in the EICLR field of the INTCLR register in the INTC. To negate the interrupt factor whose active state is level-sensitive, an external circuit that has asserted the INTx signal must be operated so that it negates INTx. However, please ensure that the level input is not negated until the specified interrupt vector (IVR) has been read. (Note) Please ensure that each setting is performed in the order of setting the active state, clearing an interrupt request, and enabling an interrupt. (Example INT0 setting to cancel Stop mode) IMCGA TMP19A64(rev1.1) 6-8 TMP19A64C1D 6.4 Interrupt Priority Arbitration (1) Seven levels of interrupt priority Seven levels of priority are available and each interrupt factor can be assigned to one of these levels. The interrupt level is set by the interrupt mode control register (IMCx) which has a 3-bit field (ILx) for level settings. The greater the value (interrupt level) set in IMCx TMP19A64(rev1.1) 6-9 TMP19A64C1D 6.5 INTC Register Table 6.5.1 INTC Register Map Address 0xFFFF_E000 0xFFFF_E004 0xFFFF_E008 0xFFFF_E00C 0xFFFF_E010 0xFFFF_E014 0xFFFF_E018 0xFFFF_E01C 0xFFFF_E020 0xFFFF_E024 0xFFFF_E028 0xFFFF_E02C 0xFFFF_E030 0xFFFF_E034 0xFFFF_E038 0xFFFF_E03C 0xFFFF_E040 0xFFFF_E060 0xFFFF_E10C Register symbol IMC0 IMC1 IMC2 IMC3 IMC4 IMC5 IMC6 IMC7 IMC8 IMC9 IMCA IMCB IMCC IMCD IMCE IMCF IVR INTCLR ILEV Register Interrupt mode control register 0 Interrupt mode control register 1 Interrupt mode control register 2 Interrupt mode control register 3 Interrupt mode control register 4 Interrupt mode control register 5 Interrupt mode control register 6 Interrupt mode control register 7 Interrupt mode control register 8 Interrupt mode control register 9 Interrupt mode control register A Interrupt mode control register B Interrupt mode control register C Interrupt mode control register D Interrupt mode control register E Interrupt mode control register F Interrupt vector register Interrupt request clear register Interrupt level register Corresponding interrupt number 3-0 7-4 11 - 8 15 - 12 19 - 16 23 - 20 27 - 24 31 - 28 35 - 32 39 - 36 43 - 40 47 - 44 51 - 48 55 - 52 59 - 56 63 - 60 (Note) Unless otherwise specified, the above registers must be 32-bit accessed for both reading and writing. TMP19A64(rev1.1) 6-10 TMP19A64C1D 6.5.1 Interrupt Vector Register (IVR) The vector of each interrupt factor to be generated is listed below. 7 6 IVR6 5 IVR5 4 IVR4 3 IVR3 2 IVR2 0 1 IVR1 0 0 IVR0 0 IVR (0xFFFF_E040) bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function IVR7 0 R 0 0 0 0 The vector of the interrupt factor generated is set. 15 0 14 0 13 0 12 R/W 0 11 0 10 0 9 0 8 IVR8 R 0 The vector of the interrupt factor generated is set. 23 bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 0 22 0 21 0 20 R/W 0 19 0 18 0 17 0 16 0 31 0 30 0 29 0 28 R/W 0 27 0 26 0 25 0 24 0 TMP19A64(rev1.1) 6-11 TMP19A64C1D 6.5.2 Interrupt Level Register 7 6 5 4 3 0 Always reads "0." 2 1 0 ILEV bit Symbol (0xFFFF_E10C) Read/Write After reset Function 0 Always reads "0." PMASK0 R 000 Interrupt mask level (previous) 0 CMASK R/W (Note 1) 000 Interrupt mask level (current) 15 bit Symbol Read/Write After reset Function 0 Always reads "0." 14 13 PMASK2 12 R 11 0 Always reads "0." 10 9 PMASK1 8 000 Interrupt mask level (previous) 2 000 Interrupt mask level (previous) 1 23 bit Symbol Read/Write After reset Function 0 Always reads "0." 22 21 PMASK4 20 R 19 0 Always reads "0." 18 17 PMASK3 16 000 Interrupt mask level (previous) 4 000 Interrupt mask level (previous) 3 31 bit Symbol Read/Write After reset Function MLEV W 0 Interrupt level change 0: Decrement the interrupt level by 1 1: Change CMASK 30 29 PMASK6 28 27 R 0 Always reads "0." 26 25 PMASK5 24 000 Interrupt mask level (previous) 6 000 Interrupt mask level (previous) 5 Note) Note) This register must be 32-bit accessed. When a new interrupt is generated, the corresponding interrupt level is stored in CMASK and any previously stored values are shifted in their mask levels such that the previous CMASK is saved in PMASK0 and PMASK0 is saved in PMASK1 and so on. Upon setting MLEV to "1," set the CMASK value simultaneously. The PMASKx values are unchanged. When Note 1) Note) TMP19A64(rev1.1) 6-12 TMP19A64C1D 6.5.3 Transition of Interrupt Mask Level The transition sequence of the interrupt level register is illustrated below. PMASK6 PMASK5 PMASK4 PMASK3 PMASK2 PMASK1 PMASK0 CMASK Interrupt processing PMASK6 PMASK5 PMASK4 PMASK3 PMASK2 PMASK1 PMASK0 New interrupt level CMASK MLEV="0" "000" PMASK6 PMASK5 PMASK4 PMASK3 PMASK2 PMASK1 PMASK0 CMASK Fig. 6.5.3 Transition of Interrupt Mask Level TMP19A64(rev1.1) 6-13 TMP19A64C1D 6.5.4 Interrupt Level Register (IMCx) The interrupt level, active state, and whether it is a factor to activate DMAC or not are set for each interrupt factor. 7 6 EIM01 5 4 DM0 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 0 is set as the activation factor 3 R 0 Always reads "0." 2 IL02 1 IL01 R/W 0 0 IL00 IMC0 (0xFFFF_E000) bit Symbol Read/Write After reset Function R 0 Always reads "0." EIM00 R/W 0 0 Selects active state of interrupt request: 00: "L" level 01: Disable 10: Disable 11: Disable Be sure to set "00." 0 0 If DM0 = 0, select the interrupt level for interrupt number 0 (software set). 000: Disable Interrupt 001 to 111: 1 to 7 If DM0 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 EIM11 13 12 DM1 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 1 to be the activation factor. 11 R 0 Always reads "0." 10 IL12 9 IL11 R/W 0 8 IL10 EIM10 R/W 0 0 Selects active state of interrupt request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0 0 If DM1 = 0, select the interrupt level for interrupt number 1 (INT0). 000: Disable Interrupt 001 to 111: 1 to 7 If DM1 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 EIM21 21 20 DM2 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 2 to be the activation factor. 19 R 0 Always reads "0." 18 IL22 17 IL21 R/W 0 16 IL20 EIM20 R/W 0 0 Selects active state of interrupt request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0 0 If DM2 = 0, select the interrupt level for interrupt number 2 (INT1). 000: Disable Interrupt 001 to 111: 1 to 7 If DM2 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 EIM31 29 28 DM3 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 3 to be the activation factor. 27 R 0 Always reads "0." 26 IL32 25 IL31 R/W 0 24 IL30 EIM30 R/W 0 0 Selects active state of interrupt request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0 0 If DM3 = 0, select the interrupt level for interrupt number 3 (INT2). 000: Disable Interrupt 001 to 111: 1 to 7 If DM3 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 TMP19A64(rev1.1) 6-14 TMP19A64C1D 7 IMC1 bit Symbol (0xFFFF_E004) Read/Write After reset Function R 0 Always reads "0." 6 EIM41 5 4 DM4 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 4 is set as the activation factor 3 R 0 Always reads "0." 2 IL42 1 IL41 R/W 0 0 IL40 EIM40 R/W 0 0 Selects active state of interrupt request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0 0 If DM4 = 0, select the interrupt level for interrupt number 4 (INT3) 000: Disable Interrupt 001 to 111: 1 to 7 If DM4 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 EIM51 13 12 DM5 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 5 to be the activation factor. 11 R 0 Always reads "0." 10 IL52 9 IL51 R/W 0 8 IL50 EIM50 R/W 0 0 Selects active state of interrupt request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0 0 If DM5 = 0, select the interrupt level for interrupt number 5 (INT4). 000: Disable Interrupt 001 to 111: 1 to 7 If DM5 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 EIM61 21 20 DM6 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 6 to be the activation factor. 19 R 0 Always reads "0." 18 IL62 17 IL61 R/W 0 16 IL60 EIM60 R/W 0 0 Selects active state of interrupt request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0 0 If DM6 = 0, select the interrupt level for interrupt number 6 (INT5). 000: Disable Interrupt 001 to 111: 1 to 7 If DM6 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 EIM71 29 28 DM7 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 7 to be the activation factor. 27 R 0 Always reads "0." 26 IL72 25 IL71 R/W 0 24 IL70 EIM70 R/W 0 0 Selects active state of interrupt request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0 0 If DM7 = 0, select the interrupt level for interrupt number 7 (INT6). 000: Disable Interrupt 001 to 111: 1 to 7 If DM7 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 TMP19A64(rev1.1) 6-15 TMP19A64C1D 7 IMC2 bit Symbol (0xFFFF_E008) Read/Write R After reset 0 Function Always reads "0." 6 EIM81 5 4 DM8 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 8 is set as the activation factor 3 R 0 Always reads "0." 2 IL82 1 IL81 R/W 0 0 IL80 EIM80 R/W 0 0 Selects active state of interrupt request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0 0 If DM8 = 0, select the interrupt level for interrupt number 8 (INT7). 000: Disable Interrupt 001 to 111: 1 to 7 If DM8 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 EIM91 13 12 DM9 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 9 to be the activation factor. 11 R 0 Always reads "0." 10 IL92 9 IL91 R/W 0 8 IL90 EIM90 R/W 0 0 Selects active state of interrupt request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0 0 If DM9 = 0, select the interrupt level for interrupt number 9 (INT8). 000: Disable Interrupt 001 to 111: 1 to 7 If DM9 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 EIMA1 21 20 DMA 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 10 to be the activation factor. 19 R 0 Always reads "0." 18 ILA2 17 ILA1 R/W 0 16 ILA0 EIMA0 R/W 0 0 Selects active state of interrupt request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0 0 If DMA = 0, select the interrupt level for interrupt number 10 (INT9). 000: Disable Interrupt 001 to 111: 1 to 7 If DMA = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 EIMB1 29 28 DMB 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 11 to be the activation factor. 27 R 0 Always reads "0." 26 ILB2 25 ILB1 R/W 0 24 ILB0 EIMB0 R/W 0 0 Selects active state of interrupt request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0 0 If DMB = 0, select the interrupt level for interrupt number 11 (INTA) 000: Disable Interrupt 001 to 111: 1 to 7 If DMB = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 TMP19A64(rev1.1) 6-16 TMP19A64C1D 7 IMC3 bit Symbol (0xFFFF_E00C) Read/Write After reset Function R 0 Always reads "0." 6 EIMC1 5 4 DMC 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 12 is set as the activation factor 3 R 0 Always reads "0." 2 ILC2 1 ILC1 R/W 0 0 ILC0 EIMC0 R/W 0 0 Selects active state of interrupt request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0 0 If DMC = 0, select the interrupt level for interrupt number 12 (INTB) 000: Disable Interrupt 001 to 111: 1 to 7 If DMC = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 EIMD1 13 12 DMD 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 13 to be the activation factor. 11 R 0 Always reads "0." 10 ILD2 9 ILD1 R/W 0 8 ILD0 EIMD0 R/W 0 0 Selects active state of interrupt request. 01: "H" level Be sure to set "01." 0 0 If DMD = 0, select the interrupt level for interrupt number 13 (KWUP) 000: Disable Interrupt 001 to 111: 1 to 7 If DMD = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 EIME1 21 20 DME 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 14 to be the activation factor. 19 R 0 Always reads "0." 18 ILE2 17 ILE1 R/W 0 16 ILE0 EIME0 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DME = 0, select the interrupt level for interrupt number 14 (INTRX0) 000: Disable Interrupt 001 to 111: 1 to 7 If DME = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 EIMF1 29 28 DMF 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 15 to be the activation factor. 27 R 0 Always reads "0." 26 ILF2 25 ILF1 R/W 0 24 ILF0 EIMF0 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DMF = 0, select the interrupt level for interrupt number 15 (INTTX0) 000: Disable Interrupt 001 to 111: 1 to 7 If DMF = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 TMP19A64(rev1.1) 6-17 TMP19A64C1D 7 IMC4 (0xFFFF_E010) bit Symbol Read/Write After reset Function R 0 Always reads "0." 6 EIM101 5 4 DM10 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 16 is set as the activation factor 3 R 0 Always reads "0." 2 IL102 1 IL101 R/W 0 0 IL100 EIM100 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM10 = 0, select the interrupt level for interrupt number 16 (INTRX1) 000: Disable Interrupt 001 to 111: 1 to 7 If DM10 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 EIM111 13 12 DM11 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 17 to be the activation factor. 11 R 0 Always reads "0." 10 IL112 9 IL111 R/W 0 8 IL110 EIM110 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM11 = 0, select the interrupt level for interrupt number 17 (INTTX1) 000: Disable Interrupt 001 to 111: 1 to 7 If DM11 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 EIM121 21 20 DM12 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 18 to be the activation factor. 19 R 0 Always reads "0." 18 IL122 17 IL121 R/W 0 16 IL120 EIM120 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM12 = 0, select the interrupt level for interrupt number 18 (INTRX2). 000: Disable Interrupt 001 to 111: 1 to 7 If DM12 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 EIM131 29 28 DM13 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 19 to be the activation factor. 27 R 0 Always reads "0." 26 IL132 25 IL131 R/W 0 24 IL130 EIM130 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM13 = 0, select the interrupt level for interrupt number 19 (INTTX2) 000: Disable Interrupt 001 to 111: 1 to 7 If DM13 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 Note: Default values of EIMxx0 and EIMxx1 are different from the values to be used. Properly set them to the specified values before use. TMP19A64(rev1.1) 6-18 TMP19A64C1D 7 IMC5 bit Symbol (0xFFFF_E014) Read/Write After reset Function R 0 Always reads "0." 6 EIM141 5 4 DM14 0 Set as DMAC activation factor. 3 2 IL142 1 IL141 R/W 0 0 IL140 EIM140 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." R 0 0 0 Always If DM14 = 0, reads "0." select the interrupt level for interrupt number 20 (INTSB1). 000: Disable Interrupt 0: Non001 to 111: 1 to 7 activation If DM14 = 1, factor select the DMAC channel. 1: Interrupt number 20 000 to 011: 0 to 3 is set as 100 to 111: 4 to 7 the activation factor 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 EIM151 13 12 DM15 0 Set as DMAC activation factor. 11 10 IL152 9 IL151 R/W 0 8 IL150 EIM150 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." R 0 0 0 Always If DM15 = 0, reads "0." select the interrupt level for interrupt number 21 (INTADHP) 000: Disable Interrupt 0: Non001 to 111: 1 to 7 activation If DM15 = 1, factor select the DMAC channel. 1: Interrupt number 21 000 to 011: 0 to 3 to be the 100 to 111: 4 to 7 activation factor. 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 EIM161 21 20 DM16 0 Set as DMAC activation factor. 19 18 IL162 17 IL161 R/W 0 16 IL160 EIM160 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." R 0 0 0 Always If DM16 = 0, reads "0." select the interrupt level for interrupt number 22 (INTADM). 000: Disable Interrupt 0: Non001 to 111: 1 to 7 activation If DM16 = 1, factor select the DMAC channel. 1: Interrupt number 22 000 to 011: 0 to 3 to be the 100 to 111: 4 to 7 activation factor. 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 EIM171 29 28 DM17 0 Set as DMAC activation factor. 27 26 IL172 25 IL171 R/W 0 24 IL170 EIM170 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." R 0 0 0 Always If DM17 = 0, reads "0." select the interrupt level for interrupt number 23 (INTTB0). 000: Disable Interrupt 0: Non001 to 111: 1 to 7 activation If DM17 = 1, factor select the DMAC channel. 1: Interrupt number 23 000 to 011: 0 to 3 to be the 100 to 111: 4 to 7 activation factor. Note: Default values of EIMxx0 and EIMxx1 are different from the values to be used. Properly set them to the specified values before use. TMP19A64(rev1.1) 6-19 TMP19A64C1D 7 IMC6 bit Symbol (0xFFFF_E018) Read/Write After reset Function R 0 Always reads "0." 6 EIM181 5 4 DM18 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 24 is set as the activation factor 3 R 0 Always reads "0." 2 IL182 1 IL181 R/W 0 0 IL180 EIM180 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM18 = 0, select the interrupt level for interrupt number 24 (INTTB1). 000: Disable Interrupt 001 to 111: 1 to 7 If DM18 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 EIM191 13 12 DM19 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 25 to be the activation factor. 11 R 0 Always reads "0." 10 IL192 9 IL191 R/W 0 8 IL190 EIM190 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM19 = 0, select the interrupt level for interrupt number 25 (INTTB2). 000: Disable Interrupt 001 to 111: 1 to 7 If DM19 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 EIM1A1 21 20 DM1A 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 26 to be the activation factor. 19 R 0 Always reads "0." 18 IL1A2 17 IL1A1 R/W 0 16 IL1A0 EIM1A0 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM1A = 0, select the interrupt level for interrupt number 26 (INTTB3). 000: Disable Interrupt 001 to 111: 1 to 7 If DM1A = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 EIM1B1 29 28 DM1B 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 27 to be the activation factor. 27 R 0 Always reads "0." 26 IL1B2 25 IL1B1 R/W 0 24 IL1B0 EIM1B0 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM1B = 0, select the interrupt level for interrupt number 27 (INTTB4). 000: Disable Interrupt 001 to 111: 1 to 7 If DM1B = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 Note: Default values of EIMxx0 and EIMxx1 are different from the values to be used. Properly set them to the specified values before use. TMP19A64(rev1.1) 6-20 TMP19A64C1D 7 IMC7 bit Symbol (0xFFFF_E01C) Read/Write After reset Function R 0 Always reads "0." 6 EIM1C1 5 4 DM1C 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 28 to be the activation factor. 3 R 0 Always reads "0." 2 IL1C2 1 IL1C1 R/W 0 0 IL1C0 EIM1C0 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM1C = 0, select the interrupt level for interrupt number 28 (INTCAPG). 000: Disable Interrupt 001 to 111: 1 to 7 If DM1C = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 EIM1D1 13 12 DM1D 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 29 to be the activation factor. 11 R 0 Always reads "0." 10 IL1D2 9 IL1D1 R/W 0 8 IL1D0 EIM1D0 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM1D = 0, select the interrupt level for interrupt number 29 (INTCOMP0). 000: Disable Interrupt 001 to 111: 1 to 7 If DM1D = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 EIM1E1 21 20 DM1E 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 30 to be the activation factor. 19 R 0 Always reads "0." 18 IL1E2 17 IL1E1 R/W 0 16 IL1E0 EIM1E0 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM1E = 0, select the interrupt level for interrupt number 30 (INTCMP1). 000: Disable Interrupt 001 to 111: 1 to 7 If DM1E = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 EIM1F1 29 28 DM1F 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 31 to be the activation factor. 27 R 0 Always reads "0." 26 IL1F2 25 IL1F1 R/W 0 24 IL1F0 EIM1F0 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM1F = 0, select the interrupt level for interrupt number 31 (INTCMP2) 000: Disable Interrupt 001 to 111: 1 to 7 If DM1F = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 Note: Default values of EIMxx0 and EIMxx1 are different from the values to be used. Properly set them to the specified values before use. TMP19A64(rev1.1) 6-21 TMP19A64C1D 7 IMC8 (0xFFFF_E020) bit Symbol Read/Write After reset Function R 0 Always reads "0." 6 EIM201 5 4 DM20 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 32 to be the activation factor. 3 R 0 Always reads "0." 2 IL202 1 IL201 R/W 0 0 IL200 EIM200 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM20 = 0, select the interrupt level for interrupt number 32 (INTCMP3) 000: Disable Interrupt 001 to 111: 1 to 7 If DM20 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 EIM211 13 12 DM21 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 33 to be the activation factor. 11 R 0 Always reads "0." 10 IL212 9 IL211 R/W 0 8 IL210 EIM210 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM21 = 0, select the interrupt level for interrupt number 33 (INTCMP4). 000: Disable Interrupt 001 to 111: 1 to 7 If DM21 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 EIM221 21 20 DM26 19 18 IL222 17 16 IL220 0 EIM220 R/W 0 0 Be sure to set "00." R 0 0 Be sure to Always set "0." reads "0." IL221 R/W 0 0 Be sure to set "00." 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 EIM231 29 28 27 R 0 Always reads "0." 26 IL232 25 IL231 R/W 0 24 IL230 EIM230 DM23 R/W 0 0 0 Selects active state of Set as interrupt request. DMAC activation factor. 11: Rising edge Be sure to set "11." 0: Non- activation factor 1: Interrupt number 35 to be the activation factor. 0 0 If DM23 = 0, select the interrupt level for interrupt number 35 (INTRX3) 000: Disable Interrupt 001 to 111: 1 to 7 If DM23 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 Note: Default values of EIMxx0 and EIMxx1 are different from the values to be used. Properly set them to the specified values before use. TMP19A64(rev1.1) 6-22 TMP19A64C1D 7 IMC9 (0xFFFF_E024) bit Symbol Read/Write After reset Function R 0 Always reads "0." 6 EIM241 5 4 DM24 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 36 to be the activation factor. 3 R 0 Always reads "0." 2 IL242 1 IL241 R/W 0 0 IL240 EIM240 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM24 = 0, select the interrupt level for interrupt number 36 (INTTX3). 000: Disable Interrupt 001 to 111: 1 to 7 If DM24 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 EIM251 13 12 DM25 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 37 to be the activation factor. 11 R 0 Always reads "0." 10 IL252 9 IL251 R/W 0 8 IL250 EIM250 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM25 = 0, select the interrupt level for interrupt number 37 INTRX4). 000: Disable Interrupt 001 to 111: 1 to 7 If DM25 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 EIM261 21 20 DM26 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 38 to be the activation factor. 19 R 0 Always reads "0." 18 IL262 17 IL261 R/W 0 16 IL260 EIM260 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM26 = 0, select the interrupt level for interrupt number 38 (INTTX4). 000: Disable Interrupt 001 to 111: 1 to 7 If DM26 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 EIM271 29 28 DM27 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 39 to be the activation factor. 27 R 0 Always reads "0." 26 IL272 25 IL271 R/W 0 24 IL270 EIM270 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM27 = 0, select the interrupt level for interrupt number 39 (INTRX5). 000: Disable Interrupt 001 to 111: 1 to 7 If DM27 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 Note: Default values of EIMxx0 and EIMxx1 are different from the values to be used. Properly set them to the specified values before use. TMP19A64(rev1.1) 6-23 TMP19A64C1D 7 IMCA bit Symbol (0xFFFF_E028) Read/Write After reset Function R 0 Always reads "0." 6 EIM281 5 4 DM28 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 40 to be the activation factor. 3 R 0 Always reads "0." 2 IL282 1 IL281 R/W 0 0 IL280 EIM280 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM28 = 0, select the interrupt level for interrupt number 40 (INTTX5). 000: Disable Interrupt 001 to 111: 1 to 7 If DM28 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 EIM291 13 12 DM29 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 41 to be the activation factor. 11 R 0 Always reads "0." 10 IL292 9 IL291 R/W 0 8 IL290 EIM290 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM29 = 0, select the interrupt level for interrupt number 41 (INTRX6). 000: Disable Interrupt 001 to 111: 1 to 7 If DM29 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 EIM2A1 21 20 DM2A 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 42 to be the activation factor. 19 R 0 Always reads "0." 18 IL2A2 17 IL2A1 R/W 0 16 IL2A0 EIM2A0 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM2A = 0, select the interrupt level for interrupt number 42 (INTTX6). 000: Disable Interrupt 001 to 111: 1 to 7 If DM2A = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 EIM2B1 29 28 DM2B 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 43 to be the activation factor. 27 R 0 Always reads "0." 26 IL2B2 25 IL2B1 R/W 0 24 IL2B0 EIM2B0 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM2B = 0, select the interrupt level for interrupt number 43 (INTTB5). 000: Disable Interrupt 001 to 111: 1 to 7 If DM2B = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 Note: Default values of EIMxx0 and EIMxx1 are different from the values to be used. Properly set them to the specified values before use. TMP19A64(rev1.1) 6-24 TMP19A64C1D 7 IMCB bit Symbol (0xFFFF_E02C) Read/Write After reset Function 6 EIM2C1 5 4 DM2C 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 44 to be the activation factor. 3 R 0 Always reads "0." 2 IL2C2 1 IL2C1 R/W 0 0 IL2C0 EIM2C0 R R/W 0 0 0 Always Selects active state of reads "0." interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM2C = 0, select the interrupt level for interrupt number 44 (INTTB6). 000: Disable Interrupt 001 to 111: 1 to 7 If DM2C = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 bit Symbol Read/Write After reset Function 14 EIM2D1 13 12 DM2D 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 45 to be the activation factor. 11 R 0 Always reads "0." 10 IL2D2 9 IL2D1 R/W 0 8 IL2D0 EIM2D0 R R/W 0 0 0 Always Selects active state of reads "0." interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM2D = 0, select the interrupt level for interrupt number 45 (INTTB7). 000: Disable Interrupt 001 to 111: 1 to 7 If DM2D = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 bit Symbol Read/Write After reset Function 22 EIM2E1 21 20 DM2E 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 46 to be the activation factor. 19 R 0 Always reads "0." 18 IL2E2 17 IL2E1 R/W 0 16 IL2E0 EIM2E0 R R/W 0 0 0 Always Selects active state of reads "0." interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM2E = 0, select the interrupt level for interrupt number 46 (INTTB8). 000: Disable Interrupt 001 to 111: 1 to 7 If DM2E = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 bit Symbol Read/Write After reset Function 30 EIM2F1 29 28 DM2F 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 47 to be the activation factor. 27 R 0 Always reads "0." 26 IL2F2 25 IL2F1 R/W 0 24 IL2F0 EIM2F0 R R/W 0 0 0 Always Selects active state of reads "0." interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM2F = 0, select the interrupt level for interrupt number 47 (INTTB9). 000: Disable Interrupt 001 to 111: 1 to 7 If DM2F = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 Note: Default values of EIMxx0 and EIMxx1 are different from the values to be used. Properly set them to the specified values before use. TMP19A64(rev1.1) 6-25 TMP19A64C1D 7 IMCC (0xFFFF_E030) bit Symbol Read/Write After reset Function R 0 Always reads "0." 6 EIM301 5 4 DM30 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 48 to be the activation factor. 3 R 0 Always reads "0." 2 IL302 1 IL301 R/W 0 0 IL300 EIM300 R/W 0 0 Selects active state of interrupt request. 01: "H" level Be sure to set "01." 0 0 If DM30 = 0, select the interrupt level for interrupt number 48 (INTTBA). 000: Disable Interrupt 001 to 111: 1 to 7 If DM30 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 EIM311 13 12 DM31 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 49 to be the activation factor. 11 R 0 Always reads "0." 10 IL312 9 IL311 R/W 0 8 IL310 EIM310 R/W 0 0 Selects active state of interrupt request. 1: Rising edge Be sure to set "11." 0 0 If DM31 = 0, select the interrupt level for interrupt number 49 (INTCMP5) 000: Disable Interrupt 001 to 111: 1 to 7 If DM31 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 EIM321 21 20 DM32 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 50 to be the activation factor. 19 R 0 Always reads "0." 18 IL322 17 IL321 R/W 0 16 IL320 EIM320 R/W 0 0 Selects active state of interrupt request. 1: Rising edge Be sure to set "11." 0 0 If DM32 = 0, select the interrupt level for interrupt number 50 (INTCMP6) 000: Disable Interrupt 001 to 111: 1 to 7 If DM32 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 EIM331 29 28 DM33 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 51 to be the activation factor. 27 R 0 Always reads "0." 26 IL332 25 IL331 R/W 0 24 IL330 EIM330 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM33 = 0, select the interrupt level for interrupt number 51 (INTCMP7) 000: Disable Interrupt 001 to 111: 1 to 7 If DM33 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 Note: Default values of EIMxx0 and EIMxx1 are different from the values to be used. Properly set them to the specified values before use. TMP19A64(rev1.1) 6-26 TMP19A64C1D 7 IMCD bit Symbol (0xFFFF_E034) Read/Write After reset Function R 0 Always reads "0." 6 EIM341 5 4 DM34 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 52 to be the activation factor. 3 R 0 Always reads "0." 2 IL342 1 IL341 R/W 0 0 IL340 EIM340 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM34 = 0, select the interrupt level for interrupt number 52 (INTCMP8) 000: Disable Interrupt 001 to 111: 1 to 7 If DM34 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 EIM351 13 12 DM35 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 53 to be the activation factor. 11 R 0 Always reads "0." 10 IL352 9 IL351 R/W 0 8 IL350 EIM350 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM35 = 0, select the interrupt level for interrupt number 53 (INTCMP9) 000: Disable Interrupt 001 to 111: 1 to 7 If DM35 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 EIM361 21 20 DM36 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 54 to be the activation factor. 19 R 0 Always reads "0." 18 IL362 17 IL361 R/W 0 16 IL360 EIM360 R/W 0 0 Selects active state of interrupt request. 01: "H" level Be sure to set "01." 0 0 If DM36 = 0, select the interrupt level for interrupt number 54 (INTRTC) 000: Disable Interrupt 001 to 111: 1 to 7 If DM36 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 EIM371 29 28 DM37 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 55 to be the activation factor. 27 R 0 Always reads "0." 26 IL372 25 IL371 R/W 0 24 IL370 EIM370 R/W 0 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11." 0 0 If DM37 = 0, select the interrupt level for interrupt number 55 (INTAD) 000: Disable Interrupt 001 to 111: 1 to 7 If DM37 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 Note: Default values of EIMxx0 and EIMxx1 are different from the values to be used. Properly set them to the specified values before use. TMP19A64(rev1.1) 6-27 TMP19A64C1D 7 IMCE bit Symbol (0xFFFF_E038) Read/Write After reset Function R 0 Always reads "0." 6 EIM381 5 4 DM38 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 56 to be the activation factor. 3 R 0 Always reads "0." 2 IL382 1 IL381 R/W 0 0 IL380 EIM380 R/W 0 0 Selects active state of interrupt request. 10: Falling edge Be sure to set "10." 0 0 If DM38 = 0, select the interrupt level for interrupt number 56 (INTDMA0) 000: Disable Interrupt 001 to 111: 1 to 7 If DM38 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 EIM391 13 12 DM39 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 57 to be the activation factor. 11 R 0 Always reads "0." 10 IL392 9 IL391 R/W 0 8 IL390 EIM390 R/W 0 0 Selects active state of interrupt request. 10: Falling edge Be sure to set "10." 0 0 If DM39 = 0, select the interrupt level for interrupt number 57 (INTDM1) 000: Disable Interrupt 001 to 111: 1 to 7 If DM39 = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 EIM3A1 21 20 DM3A 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 58 to be the activation factor. 19 R 0 Always reads "0." 18 IL3A2 17 IL3A1 R/W 0 16 IL3A0 EIM3A0 R/W 0 0 Selects active state of interrupt request. 10: Falling edge Be sure to set "10." 0 0 If DM3A = 0, select the interrupt level for interrupt number 58 (INTDMA2) 000: Disable Interrupt 001 to 111: 1 to 7 If DM3A = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 EIM3B1 29 28 DM3B 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 59 to be the activation factor. 27 R 0 Always reads "0." 26 IL3B2 25 IL3B1 R/W 0 24 IL3B0 EIM3B0 R/W 0 0 Selects active state of interrupt request. 10: Falling edge Be sure to set "10." 0 0 If DM3B = 0, select the interrupt level for interrupt number 59 (INTDMA3). 000: Disable Interrupt 001 to 111: 1 to 7 If DM3B = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 Note: Default values of EIMxx0 and EIMxx1 are different from the values to be used. Properly set them to the specified values before use. TMP19A64(rev1.1) 6-28 TMP19A64C1D 7 IMCF bit Symbol (0xFFFF_E03C) Read/Write After reset Function R 0 Always reads "0." 6 EIM3C1 5 4 DM3C 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 60 to be the activation factor. 3 2 IL3C2 1 IL3C1 R/W 0 0 IL3C0 EIM3C0 R/W 0 0 Selects active state of interrupt request. 10: Falling edge Be sure to set "10." R 0 0 0 Always If DM3C = 0, reads "0." select the interrupt level for interrupt number 60 (INTDMA4) 000: Disable Interrupt 001 to 111: 1 to 7 If DM3C = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 EIM3D1 13 12 DM3D 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 61 to be the activation factor. 11 10 IL3D2 9 IL3D1 R/W 0 8 IL3D0 EIM3D0 R/W 0 0 Selects active state of interrupt request. 10: Falling edge Be sure to set "10." R 0 0 0 Always If DM3D = 0, reads "0." select the interrupt level for interrupt number 61 (INTDMA5) 000: Disable Interrupt 001 to 111: 1 to 7 If DM3D = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 EIM3E1 21 20 DM3E 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 62 to be the activation factor. 19 18 IL3E2 17 IL3E1 R/W 0 16 IL3E0 EIM3E0 R/W 0 0 Selects active state of interrupt request. 10: Falling edge Be sure to set "10." R 0 0 0 Always If DM3E = 0, reads "0." select the interrupt level for interrupt number 62 (INTDMA6). 000: Disable Interrupt 001 to 111: 1 to 7 If DM3E = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 EIM3F1 29 28 DM3F 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 63 to be the activation factor. 27 26 IL3F2 25 IL3F1 R/W 0 24 IL3F0 EIM3F0 R/W 0 0 Selects active state of interrupt request. 10: Falling edge Be sure to set "10." R 0 0 0 Always If DM3F = 0, reads "0." select the interrupt level for interrupt number 63 (INTDMA7). 000: Disable Interrupt 001 to 111: 1 to 7 If DM3F = 1, select the DMAC channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 Note: Default values of EIMxx0 and EIMxx1 are different from the values to be used. Properly set them to the specified values before use. TMP19A64(rev1.1) 6-29 TMP19A64C1D Note 1: Please ensure that the type of active state is selected before enabling an interrupt request. Note 2: When making interrupt requests DMAC activation factors, please ensure that you put the DMAC into standby mode after setting the INTC. 6.5.5 Interrupt Request Clear Register This register is used to clear interrupt requests. Interrupt requests are cleared by setting the IVR EICLR6 5 EICLR5 4 EICLR4 3 2 1 0 INTCLR (0xFFFF_E060) bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function EICLR3 EICLR2 EICLR1 EICLR0 R/W 0 0 0 0 0 0 0 0 Set the IVR EICLR7 15 14 13 12 R 0 Always reads "0." 11 10 9 8 EICLR8 R/W 0 23 bit Symbol Read/Write After reset Function 22 21 20 19 18 17 16 R 0 Always reads "0." 31 bit Symbol Read/Write After reset Function 30 29 28 27 26 25 24 R 0 Always reads "0." (Note 1) Do not clear interrupt requests before reading the IVR value. If an interrupt request is cleared, IVR is cleared to "0." (Note 2) To make the interrupt controller (INTC) disable specified interrupt requests, perform the following steps in the order shown: Disable the processor core to accept interrupts (Status TMP19A64(rev1.1) 6-30 TMP19A64C1D 6.5.6 INTCG Registers (Interrupts to clear Stop, Sleep and Idle modes) INT0 to INTB, KWUP0 to KWUP7: STOP/SLEEP/IDLE INTRTC, INTTBA (Two-phase pulse input counter): Sleep 7 6 R 0 Always reads "0." 0 Always reads "0." 5 4 3 0 Always reads "0." 2 R 0 Always reads "0." 1 0 Always reads "0." 0 INT0EN R/W 0 INT0 Clear input IMCGA (0xFFFF_EE10) bit Symbol Read/Write After reset Function EMCG01 EMCG00 R/W 1 0 Set active state of INT0 standby clear request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0: Disable 1: Enable 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 0 Always reads "0." 13 12 11 0 Always reads "0." 10 R 0 Always reads "0." 9 0 Always reads "0." 8 INT1EN R/W 0 INT1 Clear input EMCG11 EMCG10 R/W 1 0 Set active state of INT1 standby clear request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0: Disable 1: Enable 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 0 Always reads "0." 21 20 19 0 Always reads "0." 18 R 0 Always reads "0." 17 0 Always reads "0." 16 INT2EN R/W 0 INT2 Clear input EMCG21 EMCG20 R/W 1 0 Set active state of INT2 standby clear request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0: Disable 1: Enable 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 0 Always reads "0." 29 28 27 0 Always reads "0." 26 R 0 Always reads "0." 25 0 Always reads "0." 24 INT3EN R/W 0 INT3 Clear input EMCG31 EMCG30 R/W 1 0 Set active state of INT3 standby clear request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0: Disable 1: Enable TMP19A64(rev1.1) 6-31 TMP19A64C1D 7 IMCGB (0xFFFF_EE14) bit Symbol Read/Write After reset Function R 0 Always reads "0." 6 0 Always reads "0." 5 4 3 0 Always reads "0." 2 R 0 Always reads "0." 1 0 Always reads "0." 0 INT4EN R/W 0 INT4 Clear input EMCG41 EMCG40 R/W 1 0 Set active state of INT4 standby clear request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0: Disable 1: Enable 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 0 Always reads "0." 13 12 11 0 Always reads "0." 10 R 0 Always reads "0." 9 0 Always reads "0." 8 INT5EN R/W 0 INT5 Clear input EMCG51 EMCG50 R/W 1 0 Set active state of INT5 standby clear request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0: Disable 1: Enable 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 0 Always reads "0." 21 20 19 0 Always reads "0." 18 R 0 Always reads "0." 17 0 Always reads "0." 16 INT6EN R/W 0 INT6 Clear input EMCG61 EMCG60 R/W 1 0 Set active state of INT6 standby clear request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0: Disable 1: Enable 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 0 Always reads "0." 29 28 27 0 Always reads "0." 26 R 0 Always reads "0." 25 0 Always reads "0." 24 INT7EN R/W 0 INT7 Clear input EMCG71 EMCG70 R/W 1 0 Set active state of INT7 standby clear request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0: Disable 1: Enable TMP19A64(rev1.1) 6-32 TMP19A64C1D 7 IMCGC (0xFFFF_EE18) bit Symbol Read/Write After reset Function R 0 Always reads "0." 6 0 Always reads "0." 5 4 3 0 Always reads "0." 2 R 0 Always reads "0." 1 0 Always reads "0." 0 INT8EN R/W 0 INT8 Clear input EMCG81 EMCG80 R/W 1 0 Set active state of INT8 standby clear request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0: Disable 1: Enable 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 0 Always reads "0." 13 12 11 0 Always reads "0." 10 R 0 Always reads "0." 9 0 Always reads "0." 8 INT9EN R/W 0 INT9 Clear input EMCG91 EMCG90 R/W 1 0 Set active state of INT9 standby clear request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0: Disable 1: Enable 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 0 Always reads "0." 21 20 19 0 Always reads "0." 18 R 0 Always reads "0." 17 0 Always reads "0." 16 INTAEN R/W 0 INTA Clear input EMCGA1 EMCGA0 R/W 1 0 Set active state of INTA standby clear request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0: Disable 1: Enable 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 0 Always reads "0." 29 28 27 0 Always reads "0." 26 R 0 Always reads "0." 25 0 Always reads "0." 24 INTBEN R/W 0 INTB Clear input EMCGB1 EMCGB0 R/W 1 0 Set active state of INTB standby clear request. 00: "L" level 01: "H" level 10: Falling edge 11: Rising edge 0: Disable 1: Enable TMP19A64(rev1.1) 6-33 TMP19A64C1D 7 IMCGD (0xFFFF_EE1C) bit Symbol Read/Write After reset Function R 0 Always reads "0." 6 0 Always reads "0." 5 4 3 0 Always reads "0." 2 R 0 Always reads "0." 1 0 Always reads "0." 0 KWUPEN R/W 0 KWUP Clear input 0: Disable 1: Enable EMCGC1 EMCGC0 R/W 1 0 Set active state of KWUP standby clear request. 01: "H" level Be sure to set "01." 15 bit Symbol Read/Write After reset Function R 0 Always reads "0." 14 0 Always reads "0." 13 12 11 0 Always reads "0." 10 R 0 Always reads "0." 9 0 Always reads "0." 8 INTRTCEN R/W 0 INTRTC Clear input 0: Disable 1: Enable EMCGD1 EMCGD0 R/W 1 0 Set active state of INTRTC standby clear request. 11: Rising edge Be sure to set "11." 23 bit Symbol Read/Write After reset Function R 0 Always reads "0." 22 0 Always reads "0." 21 20 19 18 R 0 Always reads "0." 17 16 INTTBAEN R/W 0 INTTBA Clear input 0: Disable 1: Enable EMCGE1 EMCGE0 R/W 1 0 Set active state of INTTBA standby clear request. 11: Rising edge Be sure to set "11." Always reads "0." Always reads "0." 31 bit Symbol Read/Write After reset Function R 0 Always reads "0." 30 0 Always reads "0." 29 R/W 1 Undefined 28 0 27 26 R 0 Always reads "0." 25 24 R/W 0 Write "1." Always reads "0." Always reads "0." Note: In IMCGD, the initial value to request clearing of the Standby mode is different from the setting to be made in an operation condition. Be sure to set appropriate parameters before it is used to clear the Standby mode. TMP19A64(rev1.1) 6-34 TMP19A64C1D Be sure to set active state of the clear request if interrupt is enabled for clearing the Stop, Sleep, or Idle standby mode. (Note1) When using interrupts, be sure to follow the following sequence of action: If shared with other general ports, enable the target interrupt input. Set active state, etc., upon initialization. Clear interrupt requests. Enable interrupts (Note 2) Settings must be performed while interrupts are disabled. (Note 3) For clearing the Stop, Sleep and Idle modes with TMP19A64, 15 factors, i.e., INT0 to INTB, INTRTC, INTTBA, and KWUP (KWUP0 to 7) are available as clearing interrupts. Whether or not INT0 to INTB are to be used as clearing interrupts as well as active state edge/level selection is set with CG. Whether or not KWUP0 to 7 are to be used as STOP/SLEEP/IDLE clearing interrupts is set with CG and active state edge/level selection is set with KWUPSTn TMP19A64(rev1.1) 6-35 TMP19A64C1D EICRCG (0xFFFF_EE20) bit Symbol Read/Write After reset Function 7 0 6 5 4 0 3 ICRCG3 2 ICRCG2 1 ICRCG1 W/R 0 0 ICRCG0 0 R 0 0 Always reads "0." 0 0 Always reads "0." Clear interrupt requests. 0000: INT0 0101: INT5 0001: INT1 0110: INT6 0010: INT2 0111: INT7 0011: INT3 1000: INT8 0100: INT4 1001: INT9 1111: reserved 1010: INTA 1011: INTB 1100: KWUP 1101: INTRTC 1110: INTTBA 15 bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 0 14 0 13 0 12 11 10 0 9 0 8 0 R 0 0 Always reads "0." 23 0 22 0 21 0 20 19 18 0 17 0 16 0 R 0 0 Always reads "0." 31 0 30 0 29 0 28 27 26 0 25 0 24 0 R 0 0 Always reads "0." (Note 5) To clear interrupt request of the above 15 factors that are assigned to clear Stop/Sleep/Idle modes, For KWUP, use KWUPST For INT0 to INTB, INTTBA and INTRTC use the EICRCG register in the above CG block and then use the INTCLR register in the INTC block (two locations). For clearing any other interrupt requests, only INTCLR register is to be cleared. TMP19A64(rev1.1) 6-36 TMP19A64C1D NMIFLG (0xFFFF_EE24) bit Symbol Read/Write After reset Function 7 0 6 0 5 0 Always reads "0." 4 R 0 3 0 2 NMI 0 NMI factor 1: NMI generated by NMI pin input 1 WDT 0 NMI factor 1: NMI generated by WDT interrupt 0 WBER 0 NMI factor 1: NMI generated by write bus error 15 bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 0 14 0 13 0 12 11 10 0 9 0 8 0 R 0 0 Always reads "0." 23 0 22 0 21 0 20 19 18 0 17 0 16 0 R 0 0 Always reads "0." 31 0 30 0 29 0 28 27 26 0 25 0 24 0 R 0 0 Always reads "0." * NMI, WDT and WBER are cleared to "0" when they are read. TMP19A64(rev1.1) 6-37 TMP19A64C1D 7. 7.1 Input/Output Ports Port 0 (P00 through P07) The port 0 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register P0CR. A reset allows all bits of P0CR to be cleared to "0" and the port 0 to be put in input mode. Besides the general-purpose input/output function, the port 0 performs other functions: D0 through D7 function as a data bus and AD0 through AD7 function as an address data bus. When external memory is accessed, the port 0 automatically functions as either a data bus or an address data bus, and all bits of P0CR are cleared to "0." If the BUSMD pin is set to "L" level during a reset, the port 0 is put in separate bus mode (D0 to D7). If it is set to "H" level during a reset, the port 0 is put in multiplexed mode (AD0 to AD7). When output externally During external access 1 0 Selector Direction control (in units of bits) P0CR D0-D7/ AD0-AD7 Selector Internal data bus 1 Output latch 0 P0 STOP MODE SYSCR2 Output buffer Port 0 P00 through P07 (D0 through D7) (AD0 through AD7) S Selector 1 0 EBIF Reset Y P0 read External read Fig. 7.1.1 Port 0 (P00 through P07) TMP19A64 (rev1.1) 7-1 TMP19A64C1D Port 0 register 7 P0 (0xFFFF_F000) Bit Symbol Read/Write After reset P07 6 P06 5 P05 4 P04 3 P03 2 P02 1 P01 0 P00 R/W Input mode (output latch register is cleared to "0.") Port 0 control register 7 P0CR (0xFFFF_F002) Bit Symbol Read/Write After reset Function P07C 0 6 P06C 0 5 P05C 0 4 P04C R/W 0 3 P03C 0 2 P02C 0 1 P01C 0 0 P00C 0 0: Input 1: Output (When an external area is accessed, D7-0 or AD7-0 is used and this register is cleared to "0.") Fig. 7.1.2 Port 0 Registers TMP19A64 (rev1.1) 7-2 TMP19A64C1D 7.2 Port 1 (P10 through P17) The port 1 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register P1CR and the function register P1FC. A reset allows all bits of the output latch P1, P1CR and P1FC to be cleared to "0" and the port 1 to be put in input mode. Besides the general-purpose input/output function, the port 1 performs other functions: D8 through D15 function as a data bus, AD8 through AD15 function as an address data bus, and A8 through A15 function as an address bus. To access external memory, the port 1 must be designated as an address bus or address data bus by making proper P1CR and P1FC settings. If the BUSMD pin is set to "L" level during a reset, the port 1 is put in separate bus mode (D8 to D15). If it is set to "H" level during a reset, the port 1 is put in multiplexed mode (AD8 to AD15 or A8 to A15). When output external Direction control (in units of bits) P1CR 0 STOP MODE SYSCR2 1 Function control (in units of bits) P1FC AD8 through D15/ A8 through A15 Selector Selector Internal data bus 1 Output latch 0 P1 Port 1 P10 through P17 (D8 through D15) (AD8 through AD15/A8 through A15) Reset S Selector 1 0 EBIF Y P1 read External read Fig. 7.2.1 Port 1 (P10 through P17) TMP19A64 (rev1.1) 7-3 TMP19A64C1D Port 1 register 7 P1 (0xFFFF_F001) Bit Symbol Read/Write After reset P17 6 P16 5 P15 4 P14 3 P13 2 P12 1 P11 0 P10 R/W Input mode (output latch register is cleared to "0.") Port 1 control register 7 P1CR (0xFFFF_F004) Bit Symbol Read/Write After reset Function P17C 0 6 P16C 0 5 P15C 0 4 P14C 3 P13C 2 P12C 0 1 P11C 0 0 P10C 0 R/W 0 0 << See P1FC >> Port 1 function register 7 P1FC (0xFFFF_F005) Bit Symbol Read/Write After reset Function P17F 0 6 P16F 0 5 P15F 0 4 P14F R/W 0 3 P13F 0 2 P12F 0 1 P11F 0 0 P10F 0 P1FC/P1CR = 00: Input, 01: Output, 10: D15 through 8 or AD15 through 8, 11: A15 through 8 Function POR1 input setting POR1 output setting Separate bus mode (BUSMD="0") Data bus (D15 through D8) input/output setting Address bus (A15 through A8) output setting Address data bus (AD15 through AD8) input/output setting Address bus (A15 through A8) output setting Corresponding BIT of P1FC 0 0 1 1 1 1 Corresponding BIT of P1CR 0 1 0 PORT to be used PORT1 PORT1 PORT1 1 0 PORT1 1 Multiplexed bus mode (BUSMD="1") Fig. 7.2.2 Port 1 Registers TMP19A64 (rev1.1) 7-4 TMP19A64C1D 7.3 Port 2 (P20 through P27) The port 2 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register P2CR and the function register P2FC. A reset allows all bits of the output latch P2 to be set to "1," all bits of P2CR and P2FC to be cleared to "0," and the port 2 to be put in input mode. Besides the general-purpose input/output port function, the port 2 performs another function: A0 through A7 function as one address bus and A16 through A23 function as the other address bus. To access external memory, registers P2CR and P2FC must be provisioned to allow the port 2 to function as an address bus. If the BUSMD pin is set to "L" level during a reset, the port 2 is put in separate mode (A16 to A23). If it is set to "H" level during a reset, the port 2 is put in multiplexed mode (A0 through A7 or A16 through A23). During external access Direction control (in units of bits) P2CR STOP MODE SYSCR2 1 Function control (in units of bits) P2FC A16 through A23/ A0 through A7 Selector Selector 0 Internal data bus Output latch P2 1 0 Port 2 P20 through P27 (A16 through A23) (A0 through A7/A16 through A23) RESET S Selector 1 0 Y P2 read Fig. 7.3.1 Port 2 (P20 through P27) TMP19A64 (rev1.1) 7-5 TMP19A64C1D Port 2 register 7 P2 (0xFFFF_F012) Bit Symbol Read/Write After reset P27 6 P26 5 P25 4 P24 3 P23 2 P22 1 P21 0 P20 R/W Input mode (output latch register is cleared to "1.") Port 2 control register 7 P2CR (0xFFFF_F014) Bit Symbol Read/Write After reset Function P27C 0 6 P26C 0 5 P25C 0 4 P24C 3 P23C 2 P22C 0 1 P21C 0 0 P20C 0 R/W 0 0 < Port 2 function register 7 P2FC (0xFFFF_F015) Bit Symbol Read/Write After reset Function P27F 0 6 P26F 0 5 P25F 0 4 P24F R/W 0 3 P23F 0 2 P22F 0 1 P21F 0 0 P20F 0 P2FC/P2CR = 00: Input, 01: Output, 10: A7 through 0, 11: A23 through 16 Function POR2 input setting POR2 output setting Address bus (A7 through A0) output setting (*1) Address bus (A23 through A16) output setting (*1) Corresponding BIT of P2FC 0 0 1 1 Corresponding BIT of P2CR 0 1 0 1 PORT to be used PORT2 PORT2 PORT2 PORT2 (*1) The same address bus (A7 through A0/A23 through A16) output settings are used in both the separate bus mode and the multiplexed bus mode (BUSMD="0," "1"). Fig. 7.3.2 Port 2 Registers TMP19A64 (rev1.1) 7-6 TMP19A64C1D 7.4 Port 3 (P30 through P37) The port 3 is a general-purpose, 8-bit input/output port (P30 and P31 are used exclusively for output). For this port, inputs and outputs can be specified in units of bits by using the control register P3CR and the function register P3FC. A reset allows the output latches P30 and 31 to be set to "1." If the BUSMD pin is at the "L" level when a reset is performed, P37 goes into separate bus mode, and the output latch is set to "1." If the BUSMD pin is at the "H" level when a reset is performed, P37 goes into multiplexed bus mode, and the output latch is cleared to "0." Bit 2 through bit 6 of P3CR (bits 0 and 1 are unused) are cleared to "0." Bit 7 of P3CR is cleared to "0" in separate bus mode and set to "1" in multiplexed bus mode. All bits of P3FC are cleared to "0," P30 and P31 generate "H," and P32 through P36 go into the input mode with a pull-up resistor after RESET is cleared. If the port 3 goes into separate bus mode, P37 is put into input mode. If the port 3 goes into multiplexed bus mode, P37 is put into output mode. Besides the general-purpose input/output port function, the port 3 inputs and outputs CPU control/status signals. If the P30 pin is set to RD signal output mode ( During external access STOP MODE SYSCR2 Function control (in units of bits) P3FC S 0 Internal data bus Selector 1 Output latch P3 0 1 P3 write S Selector P30 ( RD ) P31 ( WR ) RD , WR P3 read Fig. 7.4.1 Port 3 (P30, P31) TMP19A64 (rev1.1) 7-7 TMP19A64C1D During external access Direction control (in units of bits) P3CR STOP MODE SYSCR2 0 1 Function control (in units of bits) P3FC Internal data bus Selector Programmable pull-up S Output latch P3 0 Selector P32 ( HWR ) 1 HWR 1 Selector 0 P3 read Fig. 7.4.2 Port 3 (P32) TMP19A64 (rev1.1) 7-8 TMP19A64C1D Direction control (in units of bits) P3CR STOP MODE SYSCR2 Reset Function control (in units of bits) P3FC Internal data bus Programmable pull-up Output latch P3 Output buffer P33 (WAIT / RDY) Selector WAIT RDY 0 1 Selector 1 0 P3 read Fig. 7.4.3 Port 3 (P33) TMP19A64 (rev1.1) 7-9 TMP19A64C1D STOP MODE SYSCR2 Function control (in units of bits) P3FC Internal data bus Reset Programmable pull-up Output latch P3 P34 (BUSRQ) BUSRQ S Selector 1 Y 0 P3 read Fig. 7.4.4 Port 3 (P34) TMP19A64 (rev1.1) 7-10 TMP19A64C1D STOP MODE SYSCR2 Selector 0 1 Function control (in units of bits) P3FC Internal data bus Programmable pull-up Output latch P3 1 BUSAK Selector 0 P35 (BUSAK) Selector 1 0 P3 read Fig. 7.4.5 Port 3 (P35) TMP19A64 (rev1.1) 7-11 TMP19A64C1D During external access STOP MODE SYSCR2 Selector 0 1 Function control (in units of bits) P3FC Internal data bus Programmable pull-up Output latch P3 Selector 0 P36 (R/W) 1 R/W Selector 1 0 P3 read Fig. 7.4.6 Port 3 (P36) TMP19A64 (rev1.1) 7-12 TMP19A64C1D STOP MODE SYSCR2 Selector 0 Reset 1 Function control (in units of bits) P3FC Internal data bus Output latch P3 Selector 0 P37 (ALE) 1 ALE Selector 1 0 P3 read Fig. 7.4.7 Port 3 (P37) TMP19A64 (rev1.1) 7-13 TMP19A64C1D Port 3 register 7 P3 (0xFFFF_F018) Bit Symbol Read/Write After reset P37 To be determined according to the bus mode (*1) 6 P36 5 P35 4 P34 3 P33 R/W Output mode 2 P32 1 P31 0 P30 1 1 1 1 1 1 1 Port 3 control register 7 P3CR (0xFFFF_F01A) Bit Symbol Read/Write After reset Function P37C To be determined according to the bus mode (*1) 6 P36C 0 5 P35C R/W 0 0: Input 4 P34C 0 3 P33C 0 1: Output 2 P32C 0 1 0 R 0 Output 0 Port 3 function register 7 P3FC (0xFFFF_F01B) Bit Symbol Read/Write After reset Function P37F 0 0: PORT 1: ALE 6 P36F 0 0: PORT 1: R/W 5 P35F 0 0: PORT 1: BUSAK 4 P34F R/W 0 0: PORT 1: BUSRQ 3 P33F 0 0: PORT/ WAIT 1: PORT/ RDY 2 P32F 0 0: PORT 1: HWR 1 P31F 0 0: PORT 1: WR 0 P30F 0 0: PORT 1: RD Function RD output setting WR output setting HWR output setting WAIT input setting RDY input setting BUSRQ input setting BUSAK output setting R/W output setting ALE output setting (BUSMD = "1") Corresponding BIT of P3FC 1(*2) 1(*2) 1 0 1 1 1 1 1(*1) Corresponding BIT of P3CR - - 1 0 0 0 1 1 1 PORT to be used P30 P31 P32 P33 P34 P35 P36 P37 (*1) In separate bus mode (BUSMD="0"), ALE is not output. The port 3 functions as an input/output port based on the bit setting of the control register P3CR (*2) TMP19A64 (rev1.1) 7-14 TMP19A64C1D 7.5 Port 4 (P40 through P47) The port 4 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register P4CR and the function register P4FC. A reset allows all bits of the output latch P4 to be set to "1" and all bits of P4CR to be reset to "0." Bits of P40FC through P46FC are reset to "0." P40 through P45 goes into the input mode with a pull-up resistor, and P46 and P47 are put into input mode. Besides the general-purpose input/output port function, the ports 40 through 45 outputs chip select signals ( CS0 through CS5 ), and the port 46 functions as a SCOUT output pin for outputting external clocks. During external access STOP MODE SYSCR2 Selector 0 Reset Function control (in units of bits) P4FC Internal data bus Programmable pull-up Output latch P4 1 CS0, CS1 CS2, CS3 CS4, CS5 Selector 1 0 P4 read Fig. 7.5.1 Port 4 (P40 to P45) TMP19A64 (rev1.1) 7-15 Selector 0 P40 (CS0) P41 (CS1) P42 (CS2) P43 (CS3) P44 (CS4) P45 (CS5) TMP19A64C1D Direction control (in units of bits) P4CR STOP MODE SYSCR2 Internal data bus Output latch P4 0 Selector 1 Reset P46 (SCOUT) 1 Selector P4 read fSYS clock fSYS/2 clock fs clock T0 clock 0 Fig. 7.5.2 Port 4 (P46) TMP19A64 (rev1.1) 7-16 TMP19A64C1D STOP MODE SYSCR2 Output latch Internal data bus P4 P47 1 Selector P4 read 0 Fig. 7.5.3 Port 4 (P47) TMP19A64 (rev1.1) 7-17 TMP19A64C1D Port 4 register 7 P4 (0xFFFF_F01E) Bit Symbol Read/Write After reset 1 1 1 (Pull-Up) P47 6 P46 5 P45 4 P44 3 P43 2 P42 1 P41 0 P40 R/W Input mode 1 1 (Pull-Up) (Pull-Up) 1 (Pull-Up) 1 (Pull-Up) 1 (Pull-Up) Port 4 control register 7 P4CR (0xFFFF_F020) Bit Symbol Read/Write After reset P47C 0 6 P46C 0 5 P45C 0 4 P44C 3 P43C 2 P42C 0 1 P41C 0 0 P40C 0 R/W 0 0 0: Input 1: Output Port 4 function register 7 P4FC (0xFFFF_F021) Bit Symbol Read/Write After reset Function P47F R 0 0: PORT 6 P46F 0 5 P45F 0 4 P44F 0 0: PORT 1: CS4 3 P43F R/W 0 0: PORT 1: CS3 2 P42F 0 0: PORT 1: CS2 1 P41F 0 0: PORT 1: CS1 0 P40F 0 0: PORT 1: CS0 0: PORT 0: PORT 1: SCOUT 1: CS5 Function CS0 output setting CS1 output setting CS2 output setting CS3 output setting CS4 output setting CS5 output setting SCOUT output setting Corresponding BIT of P4FC 1 1 1 1 1 1 1 Corresponding BIT of P4CR 1 1 1 1 1 1 1 PORT to be used P40 P41 P42 P43 P44 P45 P46 Fig. 7.5.4 Port 4 Registers TMP19A64 (rev1.1) 7-18 TMP19A64C1D 7.6 Port 5 (P50 through P57) The port 5 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register P5CR and the function register P5FC. A reset allows all bits of the output latch P5 to be set to "1," all bits of P5CR and P5FC to be cleared to "0," and the port 5 to be put in input mode. The port 5 also functions as an address bus (A0 through A7). To access external memory, P5CR and P5FC must be provisioned to allow the port 5 to function as an address bus. This address bus function can be used only in separate bus mode. (To put the port 5 in separate bus mode, the BUSMD pin must be set to "L" level during a reset.) During external access Direction control (in units of bits) P5CR Selector STOP MODE SYSCR2 1 Function control (in units of bits) P5FC Reset Internal data bus A0 through A7 Output latch P5 1 Selector 0 Port 5 (P50 to P57/A0 through A7) Selector 1 0 P5 read Fig. 7.6.1 Port 5 (P50 to P57) TMP19A64 (rev1.1) 7-19 TMP19A64C1D Port 5 register 7 P5 (0xFFFF_F028) Bit Symbol Read/Write After reset P57 6 P56 5 P55 4 P54 3 P53 2 P52 1 P51 0 P50 R/W Input mode (output latch register is set to "1.") Port 5 control register 7 P5CR (0xFFFF_F02C) Bit Symbol Read/Write After reset Function P57C 0 6 P56C 0 5 P55C 0 4 P54C R/W 0 0: Input 3 P53C 0 1: Output 2 P52C 0 1 P51C 0 0 P50C 0 Port 5 function register 7 P5FC (0xFFFF_F02D) Bit Symbol Read/Write After reset Function P57F 0 0: PORT 1: A7 6 P56F 0 0: PORT 1: A6 5 P55F 0 0: PORT 1: A5 4 P54F R/W 0 0: PORT 1: A4 3 P53F 0 0: PORT 1: A3 2 P52F 0 0: PORT 1: A2 1 P51F 0 0: PORT 1: A1 0 P50F 0 0: PORT 1: A0 Function POR5 input setting POR5 output setting Address bus (A7 to A0) output setting (*1) Corresponding BIT of P5FC 0 0 1 Corresponding BIT of P5CR 0 1 1 PORT to be used PORT5 PORT5 PORT5 (*1) The same address bus (A7 through A0) output setting is used in both the separate bus mode and multiplexed bus mode (BUSMD="0," "1"). Fig. 7.6.2 Port 5 Registers TMP19A64 (rev1.1) 7-20 TMP19A64C1D 7.7 Port 6 (P60 through P67) The port 6 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register P6CR and the function register P6FC. A reset allows all bits of the output latch P6 to be set to "1," all bits of P6CR and P6FC to be cleared to "0," and the port 6 to be put in input mode. Besides the input/output port function, the port 6 performs other functions: P60 and P63 output SIO data, P61 and P64 input SIO data, P62 and P65 input and output SIO CLK or input CTS, P61 and P64 input external interrupts, and P66 and P67 output a 16-bit timer. The port 6 also functions as an address bus (A8 through A15). To access external memory, P6CR and P6FC must be provisioned to allow the port 6 to function as an address bus. The address bus function can be used only in separate bus mode. (To put the port 6 in separate bus mode, the BUSMD pin must be set to "L" level during a reset.) During external access Direction control (in units of bits) P6CR Selector STOP MODE SYSCR2 1 Function control (in units of bits) P6FC Reset Internal data bus A8 through A15 Output latch P6 1 Selector 0 Port 6 (P60 to P67/A8 through A15 ) P6 read Fig. 7.7.1 Port 6 (P60 through P67) TMP19A64 (rev1.1) 7-21 Selector 1 TMP19A64C1D Port 6 register 7 P6 (0xFFFF_F029) Bit Symbol Read/Write After reset P67 6 P66 5 P65 4 P64 3 P63 2 P62 1 P61 0 P60 R/W Input mode (output latch register is set to "1.") Port 6 control register 7 P6CR (0xFFFF_F02E) Bit Symbol Read/Write After reset Function P67C 0 6 P66C 0 5 P65C 0 4 P64C 3 P63C 2 P62C 0 1 P61C 0 0 P60C 0 R/W 0 0 0: Input 1: Output Port 6 function register 7 P6FC Bit Symbol P67F 0 0: PORT 1: A15 (0xFFFF_F02F) Read/Write After reset Function 6 P66F 0 0: PORT 1: A14 5 P65F 0 0: PORT 1: A13 4 P64F R/W 0 0: PORT 1: A12 3 P63F 0 0: PORT 1: A11 2 P62F 0 0: PORT 1: A10 1 P61F 0 0: PORT 1: A9 0 P60F 0 0: PORT 1: A8 Function POR6 input setting POR6 output setting Address bus (A15 to A8) output setting (*1) Corresponding BIT of P6F 0 0 1 Corresponding BIT of P6CR 0 1 1 PORT to be used PORT6 PORT6 PORT6 (*1) The same address bus (A15 through A8) output setting is used in both the separate bus mode and multiplexed bus mode (BUSMD="0," "1"). Fig. 7.7.2 Port 6 Registers TMP19A64 (rev1.1) 7-22 TMP19A64C1D 7.8 Port 7 (P70 through P77), Port 8 (P80 through P87) and Port 9 (P90 through P97) The ports 7, 8 and 9 are 8-bit ports and used exclusively for input. They are also used as analog input ports for the A/D converter. Inputs can be specified by using the function register PnFC. A reset allows all bits of PnFC to be cleared to "0" and the ports 7, 8 and 9 to be put in input mode. Reset Reset Function control (P7FC, P8FC, P9FC) (in units of bits) Port 7 to 9 P70 through P97 (AN0 through AN23) Internal data bus Port 7 (P7 through P9) read A/D converter AD read Fig. 7.8.1 Port 7 to 9 (P70 through P77, P80 through P87 and P90 through P97) TMP19A64 (rev1.1) 7-23 TMP19A64C1D Port 7 register 7 P7 (0xFFFF_F040) Bit Symbol Read/Write After reset P77 6 P76 5 P75 4 P74 3 P73 2 P72 1 P71 0 P70 R Input mode Port 7 function register 7 P7FC (0xFFFF_F048) Bit Symbol Read/Write After reset Function P77F 0 0: PORT 1: AN7 6 P76F 0 0: PORT 1: AN6 5 P75F 0 0: PORT 1: AN5 4 P74F R/W 0 0: PORT 1: AN4 3 P73F 0 0: PORT 1: AN3 2 P72F 0 0: PORT 1: AN2 1 P71F 0 0: PORT 1: AN1 0 P70F 0 0: PORT 1: AN0 Port 8 register 7 P8 (0xFFFF_F041) Bit Symbol Read/Write After reset P87 6 P86 5 P85 4 P84 3 P83 2 P82 1 P81 0 P80 R Input mode Port 8 function register 7 P8FC (0xFFFF_F049) Bit Symbol Read/Write After reset Function P87F 0 0: PORT 1: AN15 6 P86F 0 0: PORT 1: AN14 5 P85F 0 0: PORT 1: AN13 4 P84F R/W 0 0: PORT 1: AN12 3 P83F 0 0: PORT 1: AN11 2 P82F 0 0: PORT 1: AN10 1 P81F 0 0: PORT 1: AN9 0 P80F 0 0: PORT 1: AN8 Port 9 register 7 P9 (0xFFFF_F042) Bit Symbol Read/Write After reset P97 6 P96 5 P95 4 P94 3 P93 2 P92 1 P91 0 P90 R Input mode Port 9 function register 7 P9FC (0xFFFF_F04A) Bit Symbol Read/Write After reset Function P97F 0 0: PORT 1: AN23 6 P96F 0 0: PORT 1: AN22 5 P95F 0 0: PORT 1: AN21 4 P94F R/W 0 0: PORT 1: AN20 3 P93F 0 0: PORT 1: AN19 2 P92F 0 0: PORT 1: AN18 1 P91F 0 0: PORT 1: AN17 0 P90F 0 0: PORT 1: AN16 Function Input setting for the ports 7, 8 and 9 Input setting for AN23 through AN0 Corresponding bits of P7FC, P8FC and P9FC 0 1 Fig. 7.8.2 Registers of the Ports 7, 8 and 9 TMP19A64 (rev1.1) 7-24 TMP19A64C1D 7.9 Port A (PA0 through PA7) The port A is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PACR. A reset allows PACR to be reset to "0" and the port A to function as an input port. Besides the input/output port function, the port A performs other functions: PA2, PA5, PA6 and PA7 output a 16-bit timer, and PA0, PA1, PA3 and PA4 input a 16-bit timer and external interrupts. These functions are enabled by setting corresponding bits of PAFC to "1." A reset allows PACR and PAFC to be cleared to "0" and the port A to be put in input mode. Direction control (PACR) (in units of bits) Internal data bus Function control (PAFC) (in units of bits) STOP MODE SYSCR2 Reset Output latch (PA) PA0 (TB0IN0) / INT5 PA1 (TB0IN1) / INT6 PA3 (TB1IN0) / INT7 PA4 (TB1IN1) / INT8 S Selector PA0 (TB0IN0) / INT5 , PA1 (TB0IN1) / INT6 , PA3 (TB1IN0) / INT7 , PA4 (TB1IN1) / INT8 PA read 0 1 Fig. 7.9.1 Port A (PA0, PA1, PA3, PA4) TMP19A64 (rev1.1) 7-25 TMP19A64C1D Direction control (PACR) (in units of bits) Function control (PAFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PA) 0 Selector Timer F/F OUT TB0OUT, TB1OUT TB2OUT, TB3OUT S 1 Selector PA read 0 1 S PA2 (TB0OUT PA5 (TB1OUT) PA6 (TB2OUT) PA7 (TB3OUT) Fig. 7.9.2 Port A (PA2, PA5, PA6, PA7) TMP19A64 (rev1.1) 7-26 TMP19A64C1D Port A register 7 PA (0xFFFF_F043) Bit Symbol Read/Write After reset PA7 6 PA6 5 PA5 4 PA4 3 PA3 2 PA2 1 PA1 0 PA0 R/W Input mode (output latch register is set to "1.") Port A control register 7 PACR (0xFFFF_F047) Bit Symbol Read/Write After reset Function PA7C 0 6 PA6C 0 5 PA5C 0 4 PA4C 3 PA3C 2 PA2C 0 1 PA1C 0 0 PA0C 0 R/W 0 0 0: Input 1: Output Port A function register 7 PAFC (0xFFFF_F04B) Bit Symbol Read/Write After reset Function PA7F 0 0: PORT 1: TB3OUT 6 PA6F 0 0: PORT 1: TB2OUT 5 PA5F 0 0: PORT 1: TB1OUT 4 PA4F R/W 0 0: PORT 1: TB1IN1 / INT8 3 PA3F 0 0: PORT 1: TB1IN0 / INT7 2 PA2F 0 0: PORT 1: TB0OUT 1 PA1F 0 0: PORT 1: TB0IN1 / INT6 0 PA0F 0 0: PORT 1: TB0IN0 / INT5 Function TB0IN0 input setting INT5 input setting TB0IN1 input setting INT6 input setting TB0OUT output setting TB1IN0 input setting INT7 input setting TB1IN1 input setting INT8 input setting TB1OUT output setting TB2OUT output setting TB3OUT output setting Corresponding BIT of PAFC 1 1(*1) 1 1(*1) 1 1 1(*1) 1 1(*1) 1 1 1 Corresponding BIT of PACR 0 0 0 0 1 0 0 0 0 1 1 1 PORT to be used PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 (*1) This bit setting is used only if an interrupt must be generated to clear the STOP status and if SYSCR TMP19A64 (rev1.1) 7-27 TMP19A64C1D 7.10 Port B (PB0 through PB7) Port B is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PBCR. A reset allows PBCR to be reset to "0" and the port B to function as an input port. Besides the input/output port function, the port B performs other functions: PB0 through PB5 output a 16-bit timer, and PB6 and PB7 input a 16-bit timer. These functions are enabled by setting corresponding bits of PBFC to "1." A rest allows PBCR and PBFC to be cleared to "0" and the port B to function as an input port. Direction control (PBCR) (in units of bits) Function control (PBFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PB) 0 Selector Timer F/F OUT TB4OUT, TB5OUT TB6OUT, TB7OUT TB8OUT, TB9OUT 1 S PB0 (TB4OUT) PB1 (TB5OUT) PB2 (TB6OUT) PB3 (TB7OUT) PB4 (TB8OUT) PB5 (TB9OUT) S 1 Selector PB read 0 Fig. 7.10.1 Port B (PB0 through PB5) TMP19A64 (rev1.1) 7-28 TMP19A64C1D Direction control (PBCR) (in units of bits) Internal data bus Function control (PBFC) (in units of bits) STOP MODE SYSCR2 Reset Output latch (PB) PB6 (TBAIN0) PB7 (TBAIN1) S Selector PB read TBAIN0, TBAIN1 1 0 Fig. 7.10.2 Port B (PB6, PB7) TMP19A64 (rev1.1) 7-29 TMP19A64C1D Port B register 7 PB (0xFFFF_F050) Bit Symbol Read/Write After reset PB7 6 PB6 5 PB5 4 PB4 3 PB3 2 PB2 1 PB1 0 PB0 R/W Input mode (output latch register is set to "1.") Port B control register 7 PBCR (0xFFFF_F054) Bit Symbol Read/Write After reset Function PB7C 0 6 PB6C 0 5 PB5C 0 4 PB4C R/W 0 0: Input 3 PB3C 0 1: Output 2 PB2C 0 1 PB1C 0 0 PB0C 0 Port B function register 7 PBFC (0xFFFF_F058) Bit Symbol Read/Write After reset Function PB7F 0 0: PORT 1: TBAIN1 6 PB6F 0 0: PORT 1: TBAIN0 5 PB5F 0 0: PORT 1: TB9OUT 4 PB4F R/W 0 0: PORT 1: TB8OUT 3 PB3F 0 0: PORT 1: TB7OUT 2 PB2F 0 0: PORT 1: TB6OUT 1 PB1F 0 0: PORT 1: TB5OUT 0 PB0F 0 0: PORT 1: TB4OUT Function TB4OUT output setting TB5OUT output setting TB6OUT output setting TB7OUT output setting TB8OUT output setting TB9OUT output setting TBAIN0 input setting TBAIN1 input setting Corresponding BIT of PBFC 1 1 1 1 1 1 1 1 Corresponding BIT of PBCR 1 1 1 1 1 1 0 0 PORT to be used PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Fig. 7.10.3 Port B Registers TMP19A64 (rev1.1) 7-30 TMP19A64C1D 7.11 Port C (PC0 to PC7) Port C is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PCCR. A reset allows PCCR to be reset to "0" and the port C to function as an input port. Besides the input/output port function, the port C performs other functions: PC0, PC3 and PC6 output SIO data, PC1, PC4 and PC7 input SIO data, and PC2 and PC5 input and output SIO CLK or input CTS. These functions are enabled by setting corresponding bits of PCFC to "1." A reset allows PCCR and PCFC to be cleared to "0" and the port C to function as an input port. Direction control (PCCR) (in units of bits) Function control (PCFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PC) 0 S Selector TXD0 output TXD1 output TXD2 output 1 Open drain setting possible S Selector PC read 0 1 PCODE PC0 (TXD0) PC3 (TXD1) PC6 (TXD2) Fig. 7.11.1 Port C (PC0, PC3, PC6) TMP19A64 (rev1.1) 7-31 TMP19A64C1D Direction control (PCCR) (in units of bits) Internal data bus Function control (PCFC) (in units of bits) STOP MODE SYSCR2 Reset Output latch (PC) PC1 (RXD0) PC4 (RXD1) PC7 (RXD2) S Selector RXD0 input RXD1 input RXD2 input PC read 0 1 Fig. 7.11.2 Port C (PC1, PC4, PC7) TMP19A64 (rev1.1) 7-32 TMP19A64C1D Direction control (PCCR) (in units of bits) Function control (PCFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PC) 0 S Selector SCLK0 output SCLK1 output 1 Open drain setting possible PCODE PC2 (SCLK0/CTS0) PC5 (SCLK1/CTS1) S Selector PC read CTS0, CTS1 SCLK0, SCLK1 1 0 Fig. 7.11.3 Port C (PC2, PC5) TMP19A64 (rev1.1) 7-33 TMP19A64C1D Port C register 7 PC (0xFFFF_F051) Bit Symbol Read/Write After reset PC7 6 PC6 5 PC5 4 PC4 3 PC3 2 PC2 1 PC1 0 PC0 R/W Input mode (output latch register is set to "1.") Port C control register 7 PCCR (0xFFFF_F055) Bit Symbol Read/Write After reset Function PC7C 0 6 PC6C 0 5 PC5C 0 4 PC4C R/W 0 0: Input 3 PC3C 0 1: Output 2 PC2C 0 1 PC1C 0 0 PC0C 0 Port C function register 7 PCFC (0xFFFF_F059) Bit Symbol Read/Write After reset Function PC7F 0 0: PORT 1: RXD2 6 PC6F 0 0: PORT 1: TXD2 5 PC5F 0 0: PORT 1: SCLK1 / CTS1 4 PC4F R/W 0 0: PORT 1: RXD1 3 PC3F 0 0: PORT 1: TXD1 2 PC2F 0 0: PORT 1: SCLK0 / CTS0 1 PC1F 0 0: PORT 1: RXD0 0 PC0F 0 0: PORT 1: TXD0 Port C open drain control register 7 PCODE (0xFFFF_F05D) Bit Symbol Read/Write After reset Function R 0 0: CMOS 6 PC6ODE 0 0: CMOS 1: Open drain 5 PC5ODE 0 0: CMOS 1: Open drain 4 R 0 0: CMOS 3 PC3ODE 0 0: CMOS 1: Open drain 2 PC2ODE 0 0: CMOS 1: Open drain 1 R 0 0: CMOS 0 PC0ODE R/W 0 0: CMOS 1: Open drain R/W R/W Function TXD0 output setting RXD0 input setting SCLK0 output setting SCLK0 input setting CTS0 input setting TXD1 output setting RXD1 output setting SCLK1 output setting SCLK1 input setting CTS1 input setting TXD2 output setting RXD2 input setting Corresponding BIT of PCFC 1 1 1 1 1 1 1 1 1 1 1 1 Corresponding BIT of PCCR 1 0 1 0 0 1 1 1 0 0 0 0 PORT to be used PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 Fig. 7.11.4 Port C Registers TMP19A64 (rev1.1) 7-34 TMP19A64C1D 7.12 Port D (PD0 to PD7) The port D is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PDCR. A reset allows PDCR to be reset to "0" and the port D to function as an input port. Besides the input/output port function, the port D performs other functions: PD0, PD3 and PD6 input and output SIO CLK or input CTS, PD1 and PD4 output SIO data, PD2 and PD5 input SIO data, and PD7 inputs external interrupts. These functions are enabled by setting corresponding bits of PDFC to "1." A reset allows PDCR and PDFC to be cleared to "0" and the port D to function as an input port. Direction control (PDCR) (in units of bits) Function control (PDFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PD) 0 SCLK2 output SCLK3 output SCLK4 output S Selector 1 Open drain setting possible S Selector PD read CTS2, CTS3 CTS4 SCLK2, SCLK3 SCLK4 0 1 PDODE PD0 (SCLK2/CTS2) PD3 (SCLK3/CTS3) PD6 (SCLK4/CTS4) Fig. 7.12.1 Port D (PD0, PD3, PD6) TMP19A64 (rev1.1) 7-35 TMP19A64C1D Direction control (PDCR) (in units of bits) Function control (PDFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PD) 0 S Selector TXD3 output TXD4 output 1 Open drain setting possible S Selector PD read 0 1 PDODE PD1 (TXD3) PD4 (TXD4) Fig. 7.12.2 Port D (PD1, PD4) TMP19A64 (rev1.1) 7-36 TMP19A64C1D Direction control (PDCR) (in units of bits) Internal data bus Function control (PDFC) (in units of bits) STOP MODE SYSCR2 Reset Output latch (PD) PD2 (RXD3) PD5 (RXD4) S Selector PD read RXD3 input RXD4 input 1 0 Fig. 7.12.3 Port D (PD2, PD5) TMP19A64 (rev1.1) 7-37 TMP19A64C1D Direction control (PDCR) (in units of bits) STOP MODE SYSCR2 Function control (PDFC) (in units of bits) Internal data bus Output latch (PD) PD7 (INT9) Reset S Selector PD read 0 1 INT9 Fig. 7.12.4 Port D (PD7) TMP19A64 (rev1.1) 7-38 TMP19A64C1D Port D register 7 PD (0xFFFF_F052) Bit Symbol Read/Write After reset PD7 6 PD6 5 PD5 4 PD4 3 PD3 2 PD2 1 PD1 0 PD0 R/W Input mode (output latch register is set to "1.") Port D control register 7 PDCR (0xFFFF_F056) Bit Symbol Read/Write After reset Function PD7C 0 6 PD6C 0 5 PD5C 0 4 PD4C R/W 0 0: Input 3 PD3C 0 1: Output 2 PD2C 0 1 PD1C 0 0 PD0C 0 Port D function register 7 PDFC (0xFFFF_F05A) Bit Symbol Read/Write After reset Function PD7F 0 0: PORT 1: INT9 6 PD6F 0 0: PORT 1: SCLK4 / CTS4 5 PD5F 0 0: PORT 1: RXD4 4 PD4F R/W 0 0: PORT 1: TXD4 3 PD3F 0 0: PORT 1: SCLK3 / CTS3 2 PD2F 0 0: PORT 1: RXD3 1 PD1F 0 0: PORT 1: TXD3 0 PD0F 0 0: PORT 1: SCLK2 / CTS2 Port D open drain control register 7 PDODE (0xFFFF_F05E) Bit Symbol Read/Write After reset Function R 0 0: CMOS 6 PD6ODE R/W 0 0: CMOS 1: Open 5 R 0 0: CMOS 4 PD4ODE 0 0: CMOS 1: Open 3 PD3ODE 0 0: CMOS 1: Open 2 R 0 0: CMOS 1 PD1ODE 0 0: CMOS 1: Open 0 PD0ODE 0 0: CMOS 1: Open R/W R/W drain drain drain drain drain Function SCLK2 output setting SCLK2 input setting CTS2 input setting TXD3 output setting RXD3 input setting SCLK3 output setting SCLK3 input setting CTS3 input setting TXD4 output setting RXD4 output setting SCLK4 output setting SCLK4 input setting CTS4 input setting INT9 input setting Corresponding BIT of PDFC 1 1 1 1 1 1 1 1 1 1 1 1 1 1(*1) Corresponding BIT of PDCR 1 0 0 1 0 1 0 0 1 1 1 0 0 0 PORT to be used PD0 PD1 PC2 PD3 PD4 PD5 PD6 PD7 (*1) This bit setting is used only if an interrupt must be generated to clear the STOP status and if SYSCR TMP19A64 (rev1.1) 7-39 TMP19A64C1D 7.13 Port E (PE0 through PE7) The port E is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PECR. A reset allows PECR to be reset to "0" and the port E to function as an input port. Besides the input/output port function, the port E performs other functions: PE0 outputs SIO data, PE1 inputs SIO data, PE2 inputs and outputs SIO CLK or inputs CTS, and PE6 and PE7 input external interrupts. These functions are enabled by setting corresponding bits of PEFC to "1." A reset allows PECR and PEFC to be cleared to "0" and the port E to function as an input port. Direction control (PECR) (in units of bits) Function control (PEFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PE) 0 S Selector TXD5 output 1 Open drain setting possible PEODE PE0 (TXD5) S Selector PE read 1 0 Fig. 7.13.1 Port E (PE0) TMP19A64 (rev1.1) 7-40 TMP19A64C1D Direction control (PECR) (in units of bits) Internal data bus Function control (PEFC) (in units of bits) STOP MODE SYSCR2 Reset Output latch (PE) PE1 (RXD5) S Selector PE read RXD5 input 1 0 Fig. 7.13.2 Port E (PE1) TMP19A64 (rev1.1) 7-41 TMP19A64C1D Direction control (PECR) (in units of bits) Function control (PEFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PE) 0 S Selector SCLK5 output 1 Open drain setting possible PEODE PE2 (SCLK5/CTS5) S Selector PE read CTS5 SCLK5 1 0 Fig. 7.13.3 Port E (PE2) TMP19A64 (rev1.1) 7-42 TMP19A64C1D Direction control (PECR) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PE) PE3 PE4 PE5 S Selector PE read 0 1 Fig. 7.13.4 Port E (PE3, PE4, PE5) TMP19A64 (rev1.1) 7-43 TMP19A64C1D Direction control (PECR) (in units of bits) STOP MODE SYSCR2 Function control (PEFC) (in units of bits) Internal data bus Output latch (PE) PE6 (INTA) PE7 (INTB) Reset S Selector 1 PE read 0 INTA INTB Fig. 7.13.5 Port E (PE6, PE7) TMP19A64 (rev1.1) 7-44 TMP19A64C1D Port E register 7 PE (0xFFFF_F053) Bit Symbol Read/Write After reset PE7 6 PE6 5 PE5 4 PE4 3 PE3 2 PE2 1 PE1 0 PE0 R/W Input mode (output latch register is set to "1.") Port E control register 7 PECR (0xFFFF_F057) Bit Symbol Read/Write After reset Function PE7C 0 6 PE6C 0 5 PE5C 0 4 PE4C R/W 0 0: Input 3 PE3C 0 1: Output 2 PE2C 0 1 PE1C 0 0 PE0C 0 Port E function register 7 PEFC (0xFFFF_F05B) Bit Symbol Read/Write After reset Function PE7F 0 0: PORT 1: INTB 6 PE6F 0 0: PORT 1: INTA 5 PE5F 0 0: PORT 4 PE4F R/W 0 0: PORT 3 PE3F 0 0: PORT 2 PE2F 0 0: PORT 1: SCLK5 / CTS5 1 PE1F 0 0: PORT 1: RXD5 0 PE0F 0 0: PORT 1: TXD5 Port E open drain control register 7 PEODE (0xFFFF_F05F) Bit Symbol Read/Write After reset Function 0 0: CMOS 6 5 R 0 0: CMOS 4 3 2 PE2ODE R/W 0 0: CMOS 1: Open 1 R 0 0: CMOS 0 PE0ODE R/W 0 0: CMOS 1: Open 0 0: CMOS 0 0: CMOS 0 0: CMOS drain drain Function TXD5 output setting RXD3 output setting SCLK5 output setting SCLK5 input setting CTS5 input setting INTA input setting INTB input setting Corresponding BIT of PEFC 1 1 1 1 1 1(*1) 1(*1) Corresponding BIT of PECR 1 0 1 0 0 0 0 PORT to be used PE0 PE1 PE2 PE6 PE7 (*1) This bit setting is used only if an interrupt must be generated to clear the STOP status and if SYSCR TMP19A64 (rev1.1) 7-45 TMP19A64C1D 7.14 Port F (PF0 through PF7) The port F is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PFCR. A reset allows PFCR to be reset to "0" and the port F to function as an input port. Besides the input/output port function, the port F performs other functions: PF0 through PF2 input and output SB1, PE3 and PE5 input the DMA request signal, PF4 and PF6 output the DMA acknowledge signal, and PF7 inputs external clock sources of a 32-bit time base timer. These functions are enabled by setting corresponding bits of PFFC to "1." A reset allows PFCR and PFFC to be cleared to "0" and the port F to function as an input port. The DMAC function is shared by PF3 through PF6 and PJ0 through PJ3. To give PF0 through PF3 the precedence in using the DMAC function, the corresponding bit of PFFC must be set to "1." Direction control (PFCR) (in units of bits) Function control (PFFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Output latch (PF) 0 S Selector SO output SDA output 1 Open drain setting possible PFODE PF0 (SO/SDA) Reset S Selector PF read SDA input 1 0 Fig. 7.14.1 Port F (PF0) TMP19A64 (rev1.1) 7-46 TMP19A64C1D Direction control (PFCR) (in units of bits) Function control (PFFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Output latch (PF) 0 S Selector SCL output 1 Open drain setting possible PFODE PF1 (SI/SCL) Reset S Selector PF read SI input SCL input 1 0 Fig. 7.14.2 Port F (PF1) TMP19A64 (rev1.1) 7-47 TMP19A64C1D Direction control (PFCR) (in units of bits) Function control (PFFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Output latch (PF) 0 S Selector SCK output 1 PF2 (SCK) Reset S Selector PF read SCK input 1 0 Fig. 7.14.3 Port F (PF2) TMP19A64 (rev1.1) 7-48 TMP19A64C1D Direction control (PFCR) (in units of bits) Internal data bus Function control (PFFC) (in units of bits) STOP MODE SYSCR2 Reset Output latch (PF) PF3 (DREQ2) PF5 (DREQ3) S Selector PF read DREQ2 input DREQ3 input 0 1 Fig. 7.14.4 Port F (PF3, PF5) TMP19A64 (rev1.1) 7-49 TMP19A64C1D Direction control (PFCR) (in units of bits) Function control (PFFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PF) 0 Selector DACK2 output DACK3 output S 1 Selector PF read 0 1 PF4 (DACK2) PF6 (DACK3) S Fig. 7.14.5 Port F (PF4, PF6) TMP19A64 (rev1.1) 7-50 TMP19A64C1D Direction control (PFCR) (in units of bits) Internal data bus Function control (PFFC) (in units of bits) STOP MODE SYSCR2 Reset Output latch (PF) PF7 (TBTIN) S Selector PF read TBTIN 1 0 Fig. 7.14.6 Port F (PF7) TMP19A64 (rev1.1) 7-51 TMP19A64C1D Port F register 7 PF (0xFFFF_F060) Bit Symbol Read/Write After reset PF7 6 PF6 5 PF5 4 PF4 3 PF3 2 PF2 1 PF1 0 PF0 R/W Input mode (output latch register is set to "1.") Port F control register 7 PFCR (0xFFFF_F064) Bit Symbol Read/Write After reset Function PF7C 0 6 PF6C 0 5 PF5C 0 4 PF4C R/W 0 0: Input 3 PF3C 0 1: Output 2 PF2C 0 1 PF1C 0 0 PF0C 0 Port F function register 7 PFFC (0xFFFF_F068) Bit Symbol Read/Write After reset Function PF7F 0 0: PORT 1: TBTIN 6 PF6F 0 0: PORT 1: DACK3 5 PF5F 0 0: PORT 1: DREQ3 4 PF4F R/W 0 0: PORT 1: DACK2 3 PF3F 0 0: PORT 1: DREQ2 2 PF2F 0 0: PORT 1: SCK 1 PF1F 0 0: PORT 1: SI / SCL 0 PF0F 0 0: PORT 1: SO / SDA Port F open drain control register 7 PFODE (0xFFFF_F06C) Bit Symbol Read/Write After reset Function R 0 0: CMOS 6 5 4 3 2 1 PF1ODE R/W 0 PF0ODE 0 0: CMOS 1: Open 0 0: CMOS 0 0: CMOS 0 0: CMOS 0 0: CMOS 0 0: CMOS 0 0: CMOS 1: Open drain drain Function SO output setting SDA output setting SDA input setting SI input setting SCL output setting SCL input setting SCLK5 output setting SCLK5 input setting DREQ2 input setting DACK2 output setting DREQ3 input setting DACK3 output setting TBTIN input setting Corresponding BIT of PFFC 1 1 1 1 1 1 1 1 1 1 1 1 1 Corresponding BIT of PFCR 1 1 0 0 1 0 1 0 0 1 0 1 0 PORT to be used PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 (Note) The DMAC function is shared by the port F and the port J. If both ports are set to use the DMAC function, the port F is given priority in using the DMAC function. Fig. 7.14.7 Port F Registers TMP19A64 (rev1.1) 7-52 TMP19A64C1D 7.15 Port G (PG0 through PG7) The port G is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PGCR. A reset allows PGCR to be reset to "0" and the port G to function as an input port. Besides the input/output port function, the port G performs other functions: PG0 through PG3 input a 32-bit input capture trigger, and PG4 through PG7 output a 32-bit output compare. These functions are enabled by setting corresponding bits of PGFC to "1." A reset allows PGCR and PGFC to be cleared to "0" and the port G to function as an input port. Direction control (PGCR) (in units of bits) Internal data bus Function control (PGFC) (in units of bits) STOP MODE SYSCR2 Reset Output latch (PG) PG0 (TC0IN) PG1 (TC1IN) PG2 (TC2IN) PG3 (TC3IN) S Selector PG read TC0IN, TC1IN TC2IN, TC3IN 0 1 Fig. 7.15.1 Port G (PG0 through PG3) TMP19A64 (rev1.1) 7-53 TMP19A64C1D Direction control (PGCR) (in units of bits) Function control (PGFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PG) 0 Selector Timer F/F OUT TCOUT0 TCOUT1 TCOUT2 TCOUT3 1 S PG4 (TCOUT0) PG5 (TCOUT1) PG6 (TCOUT2) PG7 (TCOUT3) S 1 Selector PG read 0 Fig. 7.15.2 Port G (PG4 through PG7) TMP19A64 (rev1.1) 7-54 TMP19A64C1D Port G register 7 PG (0xFFFF_F061) Bit Symbol Read/Write After reset PG7 6 PG6 5 PG5 4 PG4 3 PG3 2 PG2 1 PG1 0 PG0 R/W Input mode (output latch register is set to "1.") Port G control register 7 PGCR (0xFFFF_F065) Bit Symbol Read/Write After reset Function PG7C 0 6 PG6C 0 5 PG5C 0 4 PG4C R/W 0 0: Input 3 PG3C 0 1: Output 2 PG2C 0 1 PG1C 0 0 PG0C 0 Port G function register 7 PGFC (0xFFFF_F069) Bit Symbol Read/Write After reset Function PG7F 0 0: PORT 1: TCOUT3 6 PG6F 0 0: PORT 1: TCOUT2 5 PG5F 0 0: PORT 1: TCOUT1 4 PG4F R/W 0 0: PORT 1: TCOUT0 3 PG3F 0 0: PORT 1: TC3IN 2 PG2F 0 0: PORT 1: TC2IN 1 PG1F 0 0: PORT 1: TC1IN 0 PG0F 0 0: PORT 1: TC0IN Function TC0IN input setting TC1IN input setting TC2IN input setting TC3IN input setting TCOUT0 output setting TCOUT1 output setting TCOUT2 output setting TCOUT3 output setting Corresponding BIT of PGFC 1 1 1 1 1 1 1 1 Corresponding BIT of PGCR 0 0 0 0 1 1 1 1 PORT to be used PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 Fig. 7.15.2 Port G Registers TMP19A64 (rev1.1) 7-55 TMP19A64C1D 7.16 Port H (PH0 through PH7) The port H is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PHCR. A reset allows PHCR to be reset to "0" and the port H to function as an input port. Besides the input/output port function, the port H performs another function: PH0 through PH5 output the 32-bit output compare. This function is enabled by setting the corresponding bit of PHFC to "1." A reset allows PHCR and PHFC to be cleared to "0" and the port H to function as an input port. Direction control (PHCR) (in units of bits) Function control (PHFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PH) 0 Selector Timer F/F OUT TCOUT4, TCOUT5 TCOUT6, TCOUT7 TCOUT8, TCOUT9 1 S PH0 (TCOUT4) PH1 (TCOUT5) PH2 (TCOUT6) PH3 (TCOUT7) PH4 (TCOUT8) PH5 (TCOUT9) S 1 Selector PH read 0 Fig. 7.16.1 Port H (PH0 through PH5) TMP19A64 (rev1.1) 7-56 TMP19A64C1D Direction control (PHCR) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PH) PH6 PH7 S Selector PH read 1 0 Fig. 7.16.2 Port H (PH6, PH7) TMP19A64 (rev1.1) 7-57 TMP19A64C1D Port H register 7 PH (0xFFFF_F062) Bit Symbol Read/Write After reset PH7 6 PH6 5 PH5 4 PH4 3 PH3 2 PH2 1 PH1 0 PH0 R/W Input mode (output latch register is set to "1.") Port H control register 7 PHCR (0xFFFF_F066) Bit Symbol Read/Write After reset Function PH7C 0 6 PH6C 0 5 PH5C 0 4 PH4C R/W 0 0: Input 3 PH3C 0 1: Output 2 PH2C 0 1 PH1C 0 0 PH0C 0 Port H function register 7 PHFC (0xFFFF_F06A) Bit Symbol Read/Write After reset Function R 0 0: PORT 6 5 PH5F 4 PH4F 0 0: PORT 1: TCOUT8 3 PH3F R/W 0 0: PORT 1: TCOUT7 2 PH2F 0 0: PORT 1: TCOUT6 1 PH1F 0 0: PORT 1: TCOUT5 0 PH0F 0 0: PORT 1: TCOUT4 0 0: PORT 0 0: PORT 1: TCOUT9 Function TCOUT4 output setting TCOUT5 output setting TCOUT6 output setting TCOUT7 output setting TCOUT8 output setting TCOUT9 output setting Corresponding BIT of PHFC 1 1 1 1 1 1 Corresponding BIT of PHCR 1 1 1 1 1 1 PORT to be used PH0 PH1 PH2 PH3 PH4 PH5 Fig. 7.16.3 Port H Registers TMP19A64 (rev1.1) 7-58 TMP19A64C1D 7.17 Port I (PI0 through PI4) The port I is a general-purpose, 5-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PICR. A reset allows PICR to be reset to "0" and the port I to function as an input port. Besides the input/output port function, the port I performs another function: PI0 through PI4 input external interrupts. This function is enabled by setting the corresponding bit of PIFC to "1." A reset allows PICR and PIFC to be cleared to "0" and the port I to function as an input port. The external interrupt function is shared by PI0 through PI4 and PO0 through PO4. To give PO0 through PO4 the precedence in using the external interrupt function, the corresponding bit of POFC must be set to the interrupt function. Direction control (PICR) (in units of bits) STOP MODE SYSCR2 Function control (PIFC) (in units of bits) Internal data bus Output latch (PI) PI0 (INT0) PI1 (INT1) PI2 (INT2) PI3 (INT3) PI4 (INT4) Reset S Selector 1 PI read INT0 INT1 INT2 INT3 INT4 0 Fig. 7.17.1 Port I (PI0 through PI4) TMP19A64 (rev1.1) 7-59 TMP19A64C1D Port I register 7 PI (0xFFFF_F063) Bit Symbol Read/Write After reset R 6 5 4 PI4 3 PI3 2 PI2 1 PI1 0 PI0 R/W Input mode (output latch register is set to "1.") Port I control register 7 PICR (0xFFFF_F063) Bit Symbol Read/Write After reset Function 0 R 0 0 6 5 4 PI4C 0 3 PI3C 0 2 PI2C 1 PI1C 0 PI0C 0 R/W 0 0 0: Input 1: Output Port I function register 7 PIFC (0xFFFF_F06B) Bit Symbol Read/Write After reset Function 6 R 0 5 4 PI4F 3 PI3F 0 0: PORT 1: INT3 2 PI2F R/W 0 0: PORT 1: INT2 1 PI1F 0 0: PORT 1: INT1 0 PI0F 0 0: PORT 1: INT0 0 0 0 0: PORT 1: INT4 Function INT0 input setting INT1 input setting INT2 input setting INT3 input setting INT4 input setting Corresponding BIT of PIFC 1 (*1) 1 (*1) 1 (*1) 1 (*1) 1 (*1) Corresponding BIT of PICR 0 0 0 0 0 PORT to be used PI0 PI1 PI2 PI3 PI4 (Note*1) This bit setting is used only if an interrupt must be generated to clear the STOP status and if SYSCR TMP19A64 (rev1.1) 7-60 TMP19A64C1D 7.18 Port J (PJ0 through PJ3) The port J is a general-purpose, 4-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PJCR. A reset allows PJCR to be reset to "0" and the port J to function as an input port. Besides the input/output port function, the port J performs other functions: PJ0 and PJ2 input the DMA request signal, and PJ1 and PJ3 output the DMA acknowledge signal. These functions are enabled by setting the corresponding bits of PJFC to "1." A reset allows PJCR and PJFC to be cleared to "0" and the port J to function as an input port. The DMAC function is shared by PJ0 through PJ3 and PF3 through PF6. To give PF0 through PF3 the precedence in using the DMAC function over PJ0 through PJ3, the corresponding bit of PFFC must be set to "1." Direction control (PJCR) (in units of bits) Internal data bus Function control (PJFC) (in units of bits) STOP MODE SYSCR2 Reset Output latch (PJ) PJ0 (DREQ2) PJ2 (DREQ3) S Selector PJ read DREQ2 input DREQ3 input 0 1 Fig. 7.18.1 Port J (PJ0, PJ2) TMP19A64 (rev1.1) 7-61 TMP19A64C1D Direction control (PJCR) (in units of bits) Function control (PJFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PJ) 0 Selector DACK2 output DACK3 output S 1 Selector PJ read 0 1 PJ1 (DACK2) PJ3 (DACK3) S Fig. 7.18.2 Port J (PJ1, PJ3) TMP19A64 (rev1.1) 7-62 TMP19A64C1D Port J register 7 PJ (0xFFFF_F070) Bit Symbol Read/Write After reset R Input mode (output latch register is set to "1.") 6 5 4 3 PJ3 2 PJ2 R/W 1 PJ1 0 PJ0 Port J control register 7 PJCR (0xFFFF_F074) Bit Symbol Read/Write After reset Function R 0 0 0 0 0 6 5 4 3 PJ3C 2 PJ2C R/W 0 0: Input 1 PJ1C 0 1: Output 0 PJ0C 0 Port J function register 7 PJFC (0xFFFF_F078) Bit Symbol Read/Write After reset Function 6 R 5 4 3 PJ3F 2 PJ2F R/W 0 0: PORT 1: DREQ3 1 PJ1F 0 0: PORT 1: DACK2 0 PJ0F 0 0: PORT 1: DREQ2 0 0 0 0 0 0: PORT 1: DACK3 Function DREQ2 input setting DACK2 output setting DREQ3 input setting DACK3 output setting Corresponding BIT of PJFC 1 1 1 1 Corresponding BIT of PJCR 0 1 0 1 PORT to be used PJ0 PJ1 PJ2 PJ3 (Note) The DMAC function is shared by the port F and the port J. If both ports are set to use the DMAC function, the port F is given priority in using the DMAC function. Fig. 7.18.3 Port J Registers TMP19A64 (rev1.1) 7-63 TMP19A64C1D 7.19 Port K (PK0 through PK7) The port K is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PKCR. A reset allows PKCR to be reset to "0" and the port K to function as an input port. Besides the input/output port function, PK0 through PK7 perform the KEY input function. This function is enabled by setting the corresponding bit of PKFC to "1." A reset allows PKCR and PKFC to be cleared to "0" and the port K to function as an input port. The ports K0 through K7 have a pull-up resistor function. This function is enabled only if KUPPUP Direction control (PKCR) (in units of bits) STOP MODE SYSCR2 Function control (PKFC) (in units of bits) Internal data bus KUPPUP Output latch (PK) PK0 (KEY0), PK2 (KEY2), PK4 (KEY4), PK6 (KEY6), Reset S Selector 1 PK1 (KEY1) PK3 (KEY3) PK5 (KEY5) PK7 (KEY7) PK read PK0, PK2, PK4, PK6, PK1 PK3 PK5 PK7 0 Fig. 7.19.1 Port K (PK0 through PK7) TMP19A64 (rev1.1) 7-64 TMP19A64C1D Port K register 7 PK (0xFFFF_F071) Bit Symbol Read/Write After reset PK7 6 PK6 5 PK5 4 PK4 3 PK3 2 PK2 1 PK1 0 PK0 R/W Input mode (output latch register is set to "1.") Port K control register 7 PKCR (0xFFFF_F075) Bit Symbol Read/Write After reset Function PK7C 0 6 PK6C 0 5 PK5C 0 4 PK4C 3 PK3C 2 PK2C 0 1 PK1C 0 0 PK0C 0 R/W 0 0 0: Input 1: Output Port K function register 7 PKFC (0xFFFF_F079) Bit Symbol Read/Write After reset Function PK7F 0 0: PORT 1: KEY7 6 PK6F 0 0: PORT 1: KEY6 5 PK5F 0 0: PORT 1: KEY5 4 PK4F R/W 0 0: PORT 1: KEY4 3 PK3F 0 0: PORT 1: KEY3 2 PK2F 0 0: PORT 1: KEY2 1 PK1F 0 0: PORT 1: KEY1 0 PK0F 0 0: PORT 1: KEY0 Function KEY0 input setting KEY1 input setting KEY2 input setting KEY3 input setting KEY4 input setting KEY5 input setting KEY6 input setting KEY7 input setting Corresponding BIT of PKFC 1 1 1 1 1 1 1 1 Corresponding BIT of PKCR 0 0 0 0 0 0 0 0 PORT to be used PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 (*1) This bit setting is used only if an interrupt must be generated to clear the STOP status and if SYSCR TMP19A64 (rev1.1) 7-65 TMP19A64C1D 7.20 Port L (PL0 through PL7) The port L is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PLCR. A reset allows PLCR to be reset to "0" and the port L to function as an input port. Direction control (PLCR) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 Output latch (PL) S Selector PL read 1 0 Fig. 7.20.1 Port L (PL0 through PL7) TMP19A64 (rev1.1) 7-66 TMP19A64C1D Port L register 7 PL (0xFFFF_F0C0) Bit Symbol Read/Write After reset PL7 6 PL6 5 PL5 4 PL4 3 PL3 2 PL2 1 PL1 0 PL0 R/W Input mode (output latch register is set to "1.") Port L control register 7 PLCR (0xFFFF_F0C4) Bit Symbol Read/Write After reset Function PL7C 0 6 PL6C 0 5 PL5C 0 4 PL4C R/W 0 0: Input 3 PL3C 0 1: Output 2 PL2C 0 1 PL1C 0 0 PL0C 0 L () 7 PLFC Bit Symbol (0xFFFF_F0C8 Read/Write ) PL7F 6 PL6F 5 PL5F 4 PL4F R/W 3 PL3F 2 PL2F 1 PL1F 0 PL0F 0 0: PORT 1: DB7 0 0: PORT 1: DB6 0 0: PORT 1: DB5 0 0: PORT 1: DB4 0 0: PORT 1: DB3 0 0: PORT 1: DB2 0 0: PORT 1: DB1 0 0: PORT 1: DB0 7.20.2 L TMP19A64 (rev1.1) 7-67 TMP19A64C1D 7.21 Port M (PM0 through PM7) The port M is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PMCR. A reset allows PMCR to be reset to "0" and the port M to function as an input port. Direction control (PMCR) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PM) S Selector PM read 1 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 0 Fig. 7.21.1 Port M (PM0 through PM7) TMP19A64 (rev1.1) 7-68 TMP19A64C1D Port M register 7 PM (0xFFFF_F0C1) Bit Symbol Read/Write After reset PM7 6 PM6 5 PM5 4 PM4 3 PM3 2 PM2 1 PM1 0 PM0 R/W Input mode (output latch register is set to "1.") Port M control register 7 PMCR (0xFFFF_F0C5) Bit Symbol Read/Write After reset Function PM7C 0 6 PM6C 0 5 PM5C 0 4 PM4C R/W 0 0: Input 3 PM3C 0 1: Output 2 PM2C 0 1 PM1C 0 0 PM0C 0 M () 7 PMFC Bit Symbol (0xFFFF_F0C9 Read/Write ) R 0 0:PORT 6 5 PM5F 4 PM4F 3 PM3F R/W 2 PM2F 1 PM1F 0 PM0F 0 0:PORT 0 0: PORT 1: DB13 0 0: PORT 1: DB12 0 0: PORT 1: DB11 0 0: PORT 1: DB10 0 0: PORT 1: DB9 0 0: PORT 1: DB8 7.21.2 M TMP19A64 (rev1.1) 7-69 TMP19A64C1D 7.22 Port N (PN0 through PN7) The port N is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PNCR. A reset allows PNCR to be reset to "0" and the port N to function as an input port. Direction control (PNCR) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset PN0 PN1 PN2 PN3 PN4 PN5 PN6 PN7 Output latch (PN) S Selector PN read 1 0 Fig. 7.22.1 Port N (PN0 through PN7) TMP19A64 (rev1.1) 7-70 TMP19A64C1D Port N register 7 PN (0xFFFF_F0C2) Bit Symbol Read/Write After reset PN7 6 PN6 5 PN5 4 PN4 3 PN3 2 PN2 1 PN1 0 PN0 R/W Input mode (output latch register is set to "1.") Port N control register 7 PNCR (0xFFFF_F0C6) Bit Symbol Read/Write After reset Function PN7C 0 6 PN6C 0 5 PN5C 0 4 PN4C R/W 0 0: Input 3 PN3C 0 1: Output 2 PN2C 0 1 PN1C 0 0 PN0C 0 N () 7 PNFC (0xFFFF_F0C A) Bit Symbol Read/Write 6 R 5 4 3 PN3F 2 PN2F R/W 1 PN1F 0 PN0F 0 0:PORT 0 0:PORT 0 0:PORT 0 0:PORT 0 0: PORT 1:STATUS1 0 0: PORT 1:STATUS0 0 0: PORT 1: FCLK 0 0: PORT 1: BUSY 7.22.2 N TMP19A64 (rev1.1) 7-71 TMP19A64C1D 7.23 Port O (PO0 through PO7) The port O is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register POCR. Besides the input/output port function, the port O performs another function: PO0 through PO4 input external interrupts. This function is enabled by setting the corresponding bit of POFC to "1." A rest allows POCR and POFC to be cleared to "0" and the port O to function as an input port. The external interrupt function is shared by PO0 through PO4 and PI0 through PI4. To give PO0 through PO4 the precedence in using the external interrupt function, the corresponding bit of POFC must be set to the interrupt function. Direction control (POCR) (in units of bits) STOP MODE SYSCR2 Function control (POFC) (in units of bits) Internal data bus Output latch (PO) PO0 (INT0) PO1 (INT1) PO2 (INT2) PO3 (INT3) PO4 (INT4) Reset S Selector 1 PO read INT0 INT1 INT2 INT3 INT4 0 Fig. 7.23.1 Port O (PO0 through PO4) TMP19A64 (rev1.1) 7-72 TMP19A64C1D Direction control (POCR) (in units of bits) Function control (POFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PO) 0 S Selector TXD6 output 1 Open drain setting possible POODE PO5 (TXD6) S Selector PO read 1 0 Fig. 7.23.2 Port O (PO5) TMP19A64 (rev1.1) 7-73 TMP19A64C1D Direction control (POCR) (in units of bits) Internal data bus Function control (POFC) (in units of bits) STOP MODE SYSCR2 Reset Output latch (PO) PO6 (RXD6) S Selector PO read RXD6 input 1 0 Fig. 7.23.3 Port O (PO6) TMP19A64 (rev1.1) 7-74 TMP19A64C1D Direction control (POCR) (in units of bits) Function control (POFC) (in units of bits) Internal data bus STOP MODE SYSCR2 Reset Output latch (PO) 0 S Selector SCLK6 output 1 Open drain setting possible POODE PO7 (SCLK6/CTS6) S Selector PO read CTS6 SCLK6 1 0 Fig. 7.23.4 Port O (PO7) TMP19A64 (rev1.1) 7-75 TMP19A64C1D Port O register 7 PO (0xFFFF_F0C3) Bit Symbol Read/Write After reset PO7 6 PO6 5 PO5 4 PO4 3 PO3 2 PO2 1 PO1 0 PO0 R/W Input mode (output latch register is set to "1.") Port O control register 7 POCR (0xFFFF_F0C7) Bit Symbol Read/Write After reset Function PO7C 0 6 PO6C 0 5 PO5C 0 4 PO4C R/W 0 0: Input 3 PO3C 0 1: Output 2 PO2C 0 1 PO1C 0 0 PO0C 0 Port O function register 7 POFC Bit Symbol (0xFFFF_F0CB) Read/Write After reset Function 6 5 4 PO4F R/W 3 PO3F 0 0: PORT 1: INT3 2 PO2F 0 0: PORT 1: INT2 1 PO1F 0 0: PORT 1: INT1 0 PO0F 0 0: PORT 1: INT0 0 0: PORT 1: SCLK6 CTS6 0 0: PORT 1: RXD6 0 0: PORT 1: TXD6 0 0: PORT 1: INT4 Port O open drain control register 7 POODE (0xFFFF_F0CF) Bit Symbol Read/Write After reset Function PO7ODE R/W 0 0: CMOS 1: Open 6 R 0 0: CMOS 5 PO5ODE R/W 0 0: CMOS 1: Open 4 R 0 0: CMOS 3 R 0 0: CMOS 2 R 0 0: CMOS 1 R 0 0: CMOS 0 R 0 0: CMOS drain drain Function INT0 input setting INT1 input setting INT2 input setting INT3 input setting INT4 input setting TXD6 output setting RTD6 input setting SCLK6 output setting SCLK6 input setting CTS6 input setting Corresponding BIT of POFC 1(*1) 1(*1) 1(*1) 1(*1) 1(*1) 1 1 1 1 1 Corresponding BIT of POCR 0 0 0 0 0 1 0 1 0 0 PORT to be used PO0 PO1 PO2 PO3 PO4 PO5 PO6 PO7 (*1) This bit setting is used only if an interrupt must be generated to clear the STOP status and if SYSCR TMP19A64 (rev1.1) 7-76 TMP19A64C1D 7.24 Port P (PP0 through PP7) The port P is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PPCR. Besides the input/output port function, the port P performs another function: PP0 through PP7 output the signal for EJTAG. This function is enabled by a combination of the EJTAG debug level and the corresponding bit of PPFC. A reset allows PPCR and PPFC to be cleared to "0" and the port P to function as an input port. If DSU-ICE is used for debugging, the port P outputs the signal for EJTAG. Therefore, it is recommended not to use the port P as an input/output port. Direction control (PPCR) (in units of bits) EJTAG debug level STOP MODE SYSCR2 S Selector Output latch (PP) 0 1 TPD Y Output buffer PP0 (TPD0) PP1 (TPD1) PP2 (TPD2) PP3 (TPD3) PP4 (TPD4) PP5 (TPD5) PP6 (TPD6) PP7 (TPD7) Reset S 1 Selector Y 0 PP read Fig. 7.24.1 Port P (PP0 through PP7) (Note) The above system diagram does not show the debug function. TMP19A64 (rev1.1) 7-77 TMP19A64C1D Port P register 7 PP (0xFFFF_F0D0) Bit Symbol Read/Write After reset PP7 6 PP6 5 PP5 4 PP4 3 PP3 2 PP2 1 PP1 0 PP0 R/W Input mode (output latch register is set to "1.") Port P control register 7 PPCR (0xFFFF_F0D4) Bit Symbol Read/Write After reset Function PP7C 0 6 PP6C 0 5 PP5C 0 4 PP4C R/W 0 0: Input 3 PP3C 0 1: Output 2 PP2C 0 1 PP1C 0 0 PP0C 0 Port P function register 7 PPFC (0xFFFF_F0D8) Bit Symbol Read/Write After reset Function PP7F 0 6 PP6F 0 5 PP5F 0 0: PORT 1: TPD5/TPC5 4 PP4F R/W 0 0: PORT 1: TPD4/TPC4 3 PP3F 0 0: PORT 1: TPD3/TPC3 2 PP2F 0 0: PORT 1: TPD2/TPC2 1 PP1F 0 0: PORT 1: TPD1/TPC1 0 PP0F 0 0: PORT 1: TPD0/TPC0 0: PORT 0: PORT 1: TPD7/TPC7 1: TPD6/TPC6 Fig. 7.24.2 Port P Registers Note) If the port P or the port Q is used to generate the output signal for EJTAG, a necessary port P or Q setting must be made using a tool. The PPFC register setting must be made in units of bites. Level 0 PORT P PORT Q PORT PORT Level 1 PORT TPC Level 2 PPFC=#FF TPD PORT PPFC#FF PORT TPD Level 3 TPD TPC Fig. 7.24.3 Ports P and Q function relative to debug levels Note) For information on debug levels and other details, refer to the DSU Probe Handling Manual. TMP19A64 (rev1.1) 7-78 TMP19A64C1D 7.25 Port Q (PQ0 through PQ7) The port Q is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PQCR. Besides the input/output port function, PQ0 through PQ7 output the signal for EJTAG. This function is enabled by a combination of a debug level and the corresponding bit of PPFC. A reset allows PQCR and PPFC to be cleared to "0" and the port Q to function as an input port. If DSU-ICE is used for debugging, the port Q outputs the signal for EJTAG. Therefore, it is recommended not to use the port Q as an input/output port. Direction control (PQCR) (in units of bits) EJTAG debug level STOP MODE SYSCR2 S Selector Output latch (PQ) 0 1 Y Output buffer TPD/TPC PQ0 (TPD0/TPC0) PQ1 (TPD1/TPC1) PQ2 (TPD2/TPC2) PQ3 (TPD3/TPC3) PQ4 (TPD4/TPC4) PQ5 (TPD5/TPC5) PQ6 (TPD6/TPC6) PQ7 (TPD7/TPC7) Reset S 1 Selector Y 0 PP read Fig. 7.25.1 Port Q (PQ0 through PQ7) (Note) The above system diagram does not show the debug function. TMP19A64 (rev1.1) 7-79 TMP19A64C1D Port Q register 7 PQ (0xFFFF_F0D1) Bit Symbol Read/Write After reset PQ7 6 PQ6 5 PQ5 4 PQ4 3 PQ3 2 PQ2 1 PQ1 0 PQ0 R/W Input mode (output latch register is set to "1.") Port Q control register 7 PQCR (0xFFFF_F0D5) Bit Symbol Read/Write After reset Function PQ7C 0 6 PQ6C 0 5 PQ5C 0 4 PQ4C R/W 0 0: Input 3 PQ3C 0 1: Output 2 PQ2C 0 1 PQ1C 0 0 PQ0C 0 Fig. 7.25.2 Port Q Registers TMP19A64 (rev1.1) 7-80 TMP19A64C1D 8. External Bus Interface The TMP19A64 has a built-in external bus interface function to connect to external memory, I/Os, etc. This interface consists of an external bus interface circuit (EBIF), a chip selector (CS) and a wait controller. The chip selector and wait controller designate mapping addresses in a 6-block address space and also control wait states and data bus widths (8- or 16-bit) in these and other external address spaces. The external bus interface circuit (EBIF) controls the timing of external buses based on the chip selector and wait controller settings. The EBIF also controls the dynamic bus sizing and the bus arbitration with the external bus master. External bus mode Selectable address, data separator bus mode and multiplex mode Wait function This function can be enabled for each block. * * A wait of up to 7 clocks can be automatically inserted. A wait can be inserted via the WAIT / RDY pin. Data bus width Either an 8- or 16-bit width can be set for each block. Recovery cycle (read/write) If an external bus cycle is in progress, a dummy cycle of up to 2 clocks can be inserted and this dummy cycle can be specified for each block. Recovery cycle (chip selector) When an external bus is selected, a dummy cycle of up to 1 clock can be inserted and this dummy cycle can be specified for each block. Bus arbitration function TMP19A64 (rev1.1) 8-1 TMP19A64C1D 8.1 Address and Data Pins (1) Address and data pin settings The TMP19A64 can be set to either separate bus or multiplexed bus mode. Setting the BUSMD pin to the "L" level at a reset activates the separate bus mode, and setting the pin to the "H" level activates the multiplexed bus mode. Port pins 0, 1, 2, 5 and 6, which are to be connected to external devices (memory), are used as address buses, data buses and address/data buses. Table 8.1.1 shows these. Table 8.1.1 Bus Mode, Address and Data Pins Separate BUSMD="L" D0-D7 D8-D15 A16-A23 A0-A7 A8-A15 General-purpose port Multiplex BUSMD="H" AD0-AD7 AD8-AD15/A8-A15 A0-A7/A16-A23 General-purpose port General-purpose port ALE Port 0 (P00 to P07) Port 1 (P10 to P17) Port 2 (P20 to P27) Port 5 (P50 to P57) Port 6 (P60 to P67) Port 37 (P37) Each port is put into input mode after a reset. To access an external device, set the address and data bus functions by using the port control register (PnCR) and the port function register (PnFC). In the multiplex mode, the four types of functions can be selected, as shown in Table 8.1.2, by setting the port registers (PnCR and PnFC). Table 8.1.2 Address and Data Pins in the Multiplex Mode Number of address buses Number of data buses Number of address/data multiplexed buses Port 0 Port function Port 1 Port 2 max.24 (-16 MB) 8 8 AD0 to AD7 A8 to A15 A16 to A23 max.24 (-16 MB) 16 16 AD0 to AD7 AD8 to AD15 A16 to A23 max.16 (-64 KB) 8 0 AD0 to AD7 A8 to A15 A0 to A7 max.8 (-256 B) 16 0 AD0 to AD7 AD8 to AD15 A0 to A7 A23-8 A23-8 A23-16 A23-16 A15 -0 D15 -0 A15-0 AD7-0 A15-0 (Note 1) A7-0 A7-0 (Note1) A15 D15 -0 -0 Timing Diagram AD7-0 A7-0 D7-0 AD15-0 A7-0 D7-0 AD15-0 ALE ALE ALE ALE RD RD RD RD (Note 1) Even in cases of buses. and , address outputs are available as the data bus pins are also used for address (Note 2) Ports 0 to 2 are put into input modes after a reset, and they do not serve as address or data bus pins. (Note 3) Any of to can be selected by setting the P1CR, P1FC, P2CR and P2FC registers. TMP19A64 (rev1.1) 8-2 TMP19A64C1D (2) Address HOLD when an internal area is accessed When an internal area is being accessed, the address bus maintains the address output of the previously accessed external area and doesn't change it. Also, the data bus is in a state of high impedance. 8.2 Data Format Internal registers and external bus interfaces of the TMP19A64 are configured as described below. (1) Big-endian mode Word access * 16-bit bus width Internal registers address x0 x1 x2 x3 External buses D31 AA BB CC D00 DD AABB MS LS A1=0 CCDD A1=1 * 8-bit bus width Internal registers address x0 x1 x2 x3 External buses D31 AA BB CC D00 DD AA x0 BB x1 CC x2 DD x3 Half word access * 16-bit bus width Internal registers address D31 AA x0 D00 BB x1 address D31 CC x2 D00 DD x3 CCDD MS LS AABB MS LS External buses TMP19A64 (rev1.1) 8-3 TMP19A64C1D * 8-bit bus width Internal registers address D31 AA x0 D00 BB x1 A x0 B x1 External buses Internal registers address D31 CC x2 D00 DD x3 External buses C x2 D x3 Byte access * 16-bit bus width Internal registers address D31 AA MS D00 AA x0 address D31 MS D00 BB x1 address D31 CC MS D00 CC x2 address D31 MS D00 DD x3 DD LS LS BB LS LS External buses TMP19A64 (rev1.1) 8-4 TMP19A64C1D * 8-bit bus width Internal registers address D31 AA D00 AA x0 address D31 BB D00 BB x1 address D31 CC D00 CC x2 address D31 DD D00 DD x3 External buses TMP19A64 (rev1.1) 8-5 TMP19A64C1D (2) Little-endian mode Word access * 16-bit bus width Internal registers address x3 x2 x1 x0 External buses D31 DD CC BB D00 AA LS AABB MS A1=0 CCDD A1=1 * 8-bit bus width Internal registers address x3 x2 x1 x0 External buses D31 DD CC BB D00 AA AA x0 BB x1 CC x2 DD x3 Half word access * 16-bit bus width Internal registers address D31 BB x1 D00 AA x0 LS AABB MS External buses address D31 DD x3 D00 CC x2 CCDD LSB MSB TMP19A64 (rev1.1) 8-6 TMP19A64C1D * 8-bit bus width Internal registers address D31 BB x1 D00 AA x0 AA x0 BB x1 External buses Internal registers address D31 DD x3 D00 CC x2 External buses CC x2 DD x3 Byte access * 16-bit bus width Internal registers address D31 AA LSB D00 AA x0 address D31 LSB D00 BB x1 address D31 CC LSB D00 CC x2 address D31 LSB D00 DD x3 DD MSB MSB BB MSB MSB External buses TMP19A64 (rev1.1) 8-7 TMP19A64C1D * 8-bit bus width Internal registers address D31 AA D00 AA x0 address D31 BB D00 BB x1 address D31 CC D00 CC x2 address D31 DD D00 DD x3 External buses TMP19A64 (rev1.1) 8-8 TMP19A64C1D 8.3 External Bus Operations (Separate Bus Mode) This section describes various bus timing values. The timing diagram shown below assumes that the address buses are A23 through A0 and that the data buses are D15 through D0. (1) Basic bus operation The external bus cycle of the TMP19A64 basically consists of three clock pulses and a wait can be inserted as mentioned later. The basic clock of an external bus cycle is the same as the internal system clock. Fig. 8.3.1 shows read bus timing and Fig. 8.3.2 shows write bus timing. If internal areas are accessed, address buses remain unchanged as shown in these figures. Additionally, data buses are in a state of high impedance and control signals such as RD and WR do not become active. tsys CSn A [23:0] D [15:0] DATA Address HOLD Output High - Z RD External access No output of RD Internal access Fig. 8.3.1 Read Operation Timing Diagram tsys CSn A [23:0] D [15:0] DATA Address HOLD Output High - Z WR External access No output of WR Internal access Fig. 8.3.2 Write Operation Timing Diagram TMP19A64 (rev1.1) 8-9 TMP19A64C1D (2) Wait timing A wait cycle can be inserted for each block by using the chip selector (CS) and wait controller. The following three types of wait can be inserted: A wait of up to 7 clocks can be automatically inserted. A wait can be inserted via the WAIT pin (2+2N, 3+2N, 4+2N, 5+2N, 6+2N, 7+2N). Note: 2N is the number of external waits that can be inserted. A wait can be inserted via the RDY pin (2+2N, 3+2N, 4+2N, 5+2N, 6+2N, 7+2N). Note: 2N is the number of external waits that can be inserted. The setting of the number of waits to be automatically inserted and the setting of the external wait input can be made using the chip selector and wait controller registers, BmnCS Fig. 8.3.3 through Fig. 8.3.10 show the timing diagrams in which waits have been inserted. tsys A[23:0] D[15:0] RD address data address data 0 wait 1 wait Fig. 8.3.3 Read Operation Timing Diagram (0 Wait and 1 Wait Automatically Inserted) tsys A[23:0] D[15:0] RD address data 5 wait Fig. 8.3.4 Read Operation Timing Diagram (5 Waits Automatically Inserted) TMP19A64 (rev1.1) 8-10 TMP19A64C1D Fig. 8.3.5 shows the read operation timing when 0 wait, waits automatically inserted, and waits automatically inserted + external waits are inserted in the separate bus mode. tsys fsys 0 wait A[23:0] D[15:0] /RD /WAIT 2 waits automatically inserted A[23:0] D[15:0] /RD /WAIT 2 waits automatically inserted 2 waits automatically inserted + 2N (N=1) A[23:0] D[15:0] /RD /WAIT 2 waits automatically inserted 2N_WAIT 3 waits automatically inserted + 2N (N=1) A[23:0] D[15:0] /RD /WAIT 3 waits automatically inserted 2N_WAIT 2 waits automatically inserted + 2N (N=2) A[23:0] D[15:0] /RD /WAIT 2 waits automatically inserted 2N_WAIT --- External wait sampling point External wait sampling points take place before a cycle of waits automatically inserted is finished and before a 2N_wait cycle is finished as shown above. The same applies to combinations of other numbers of waits. Fig. 8.3.5 Read Operation Timing Diagram TMP19A64 (rev1.1) 8-11 TMP19A64C1D Fig. 8.3.6 shows the write operation timing when 0 wait, waits automatically inserted, and waits automatically inserted + external waits are inserted in the separate bus mode. tsys fsys 0 wait A[23:0] D[15:0] /WR /WAIT 2 waits automatically inserted A[23:0] D[15:0] /WR /WAIT 2 waits automatically inserted 2 waits automatically inserted + 2N (N=1) A[23:0] D[15:0] /WR /WAIT 3 waits automatically inserted + 2N (N=1) A[23:0] D[15:0] /WR /WAIT 2 waits automatically inserted 2N_WAIT 3 waits automatically inserted 2N_WAIT 2 waits automatically inserted + 2N (N=2) A[23:0] D[15:0] /WR /WAIT 2 waits automatically inserted 2N_WAIT --- External wait sampling point External wait sampling points take place before a cycle of waits automatically inserted is finished and before a 2N_wait cycle is finished as shown above. The same applies to combinations of other numbers of waits. Fig. 8.3.6 Write Operation Timing Diagram TMP19A64 (rev1.1) 8-12 TMP19A64C1D By setting the bit 3 tsys fsys 2 waits automatically inserted A[23:0] D[15:0] /RD /RDY 2 waits automatically inserted 2 waits automatically inserted + 2N (N=1) A[23:0] D[15:0] /RD /RDY 2 waits automatically inserted 2N_WAIT --- External RDY sampling point External RDY sampling points take place before a cycle of waits automatically inserted is finished and before a 2N_wait cycle is finished as shown above. The same applies to combinations of other numbers of waits. Fig. 8.3.7 RDY Input and Wait Operation Timing Diagram TMP19A64 (rev1.1) 8-13 TMP19A64C1D (3) Time that it takes before ALE is asserted When the external bus of the TMP19A64 is used as a multiplexed bus, the ALE width (assert time) can be specified by using the system control register SYSCR3 WR signal is different depending on the SYSCR3 During a reset, tsys A[23:0] D[15:0] RD address data address data Fig. 8.3.13 SYSCR3 TMP19A64 (rev1.1) 8-14 TMP19A64C1D (4) Recovery time If access to external areas occurs consecutively, a dummy cycle can be inserted for recovery time. A dummy cycle can be inserted in both a read and a write cycle. The dummy cycle insertion setting can be made in the chip selector and wait controller registers, BmnCS tsys CS A[23:0] RD WR No recovery cycle tsys address next address CS A[23:0] RD WR 1 recovery cycle 2 recovery cycle address next address Fig. 8.3.14 Timing of Recovery Time Insertion TMP19A64 (rev1.1) 8-15 TMP19A64C1D (5) Chip selector recovery time If access to external areas occurs consecutively, a dummy cycle can be inserted for recovery time. The dummy cycle insertion setting can be made in the chip selector and wait controller registers, BmnCS tsys CS A[23:0] RD WR No recovery cycle 1 recovery cycle address next address TMP19A64 (rev1.1) 8-16 TMP19A64C1D 8.4 External Bus Operations (Multiplexed Bus Mode) This section describes various bus timing values. The timing diagram shown below assumes that the address buses are A23 through A16 and that the address/data buses are AD15 through AD0. (1) Basic bus operation The external bus cycle of the TMP19A64 basically consists of three clock pulses and a wait can be inserted as mentioned later. The basic clock of an external bus cycle is the same as the internal system clock. Fig. 8.4.1 shows read bus timing and Fig. 8.4.2 shows write bus timing. If internal areas are accessed, address buses remain unchanged and the ALE does not output latch pulse as shown in these figures. Additionally, address/data buses are in a state of high impedance and control signals such as RD and WR do not become active. tsys CSn A [23:16] AD [15:0] ALE DATA Higher-order address HOLD Output Hi - Z ADR No output of ALE No output of RD External access Internal access RD Fig. 8.4.1 Read Operation Timing Diagram tsys CSn A [23:16] AD [15:0] ALE ADR DATA Higher-order address Output Hi - Z No output of ALE WR External area No output of WR Internal area Fig. 8.4.2 Write Operation Timing Diagram TMP19A64 (rev1.1) 8-17 TMP19A64C1D (2) Wait Timing A wait cycle can be inserted for each block by using the chip selector (CS) and wait controller. The following three types of wait can be inserted: A wait of up to 7 clocks can be automatically inserted. A wait can be inserted via the WAIT pin (2+2N, 3+2N, 4+2N, 5+2N, 6+2N, 7+2N). Note: 2N is the number of external waits that can be inserted. A wait can be inserted via the RDY pin (2+2N, 3+2N, 4+2N, 5+2N, 6+2N, 7+2N). Note: 2N is the number of external waits that can be inserted. The setting of the number of waits to be automatically inserted and the setting of the external wait input can be made using the chip selector and wait controller registers, BmnCS TMP19A64 (rev1.1) 8-18 TMP19A64C1D Fig. 8.4.3 shows the read operation timing when 0 wait, waits automatically inserted, and waits automatically inserted + external waits are inserted in the multiplexed bus mode. tsys fsys 0 wait A[23:16] AD[15:0] ALE /RD /WAIT 2 waits automatically inserted Lower-order address Higher-order address Data A[23:16] AD[15:0] ALE /RD /WAIT Lower-order address Higher-order address Data 2 waits automatically inserted 2 waits automatically inserted + 2N (N=1) A[23:16] AD[15:0] ALE /RD /WAIT Lower-order address Higher-order address Data 2 waits automatically inserted 3 waits automatically inserted + 2N (N=1) 2N_WAIT A[23:16] AD[15:0] ALE /RD /WAIT Lower-order address Higher-order address Data 3 waits automatically inserted 2 waits automatically inserted + 2N (N=2) 2N_WAIT A[23:16] AD[15:0] ALE /RD /WAIT Lower-order address Higher-order address Data 2 waits automatically inserted 2N_WAIT --- External wait sampling point External wait sampling points take place before a cycle of waits automatically inserted is finished and before a 2N_wait cycle is finished as shown above. The same applies to combinations of other numbers of waits. Fig. 8.4.3 Read Operation Timing Diagram TMP19A64 (rev1.1) 8-19 TMP19A64C1D Fig. 8.4.4 shows the write operation timing when 0 wait, waits automatically inserted, and waits automatically inserted + external waits are inserted in the multiplexed bus mode. tsys fsys 0 wait A[23:16] AD[15:0] ALE /WR /WAIT 2 waits automatically inserted Lower-order address Higher-order address Data A[23:16] AD[15:0] ALE /WR /WAIT Lower-order address Higher-order address Data 2 waits automatically inserted 2 waits automatically inserted + 2N (N=1) A[23:16] AD[15:0] ALE /WR /WAIT Lower-order address Higher-order address Data 2 waits automatically inserted 3 waits automatically inserted + 2N (N=1) 2N_WAIT A[23:16] AD[15:0] ALE /WR /WAIT Lower-order address Higher-order address Data 2 waits automatically inserted 2 waits automatically inserted + 2N (N=2) 2N_WAIT A[23:16] AD[15:0] ALE /WR /WAIT Lower-order address Higher-order address Data 2 waits automatically inserted 2N_WAIT --- External wait sampling point External wait sampling points take place before a cycle of waits automatically inserted is finished and before a 2N_wait cycle is finished as shown above. The same applies to combinations of other numbers of waits. Fig. 8.4.4 Write Operation Timing Diagram TMP19A64 (rev1.1) 8-20 TMP19A64C1D (3) Time that it takes before ALE is asserted Either 1 clock or 2 clocks can be selected as the time that it takes before ALE is asserted. The setting bit is located in the system clock control register. The default is 2 clocks. This assert setting cannot be established for each block in an external area and the same setting is commonly used in an external address space. tsys ALE (ALESEL = 0) 1 clock AD [15:0] (ALESEL = 1) 2 clocks AD [15:0] Fig. 8.4.12 Time That It Takes Before ALE Is Asserted Fig. 8.4.13 shows the timing when the ALE is 1 clock or 2 clocks. When the ALE is 1 clock or 2 clocks tsys fsys A[23:16] AD[15:0] ALE /RD Higher-order address Lower-order address Data Higher-order address Data Fig. 8.4.13 Read Operation Timing Diagram (When the ALE is 1 Clock or 2 Clocks) TMP19A64 (rev1.1) 8-21 TMP19A64C1D (4) Read and Write Recovery Time If access to external areas occurs consecutively, a dummy cycle can be inserted for recovery time. A dummy cycle can be inserted in both a read and a write cycle. The dummy cycle insertion setting can be made in the chip selector and wait controller registers, BmnCS When read/write recovery is inserted (ALE width:1fsys) tsys fsys A[23:16] AD[15:0] ALE /CS /RD,/WR Dummy cycle Normal cycle 1 recovery cycle 2 recovery cycles Dummy cycle Higher-order address Lower-order address Data Higher-order address Lower-order address Data Higher-order address Lower-order address Data Fig. 8.4.14 Timing of Recovery Time Insertion TMP19A64 (rev1.1) 8-22 TMP19A64C1D (5) Chip selector recovery time If access to external areas occurs consecutively, a dummy cycle can be inserted for recovery time. The dummy cycle insertion setting can be made in the chip selector and wait controller registers, BmnCS When chip selector recovery is inserted (ALE width:1fsys) tsys fsys A[23:16] AD[15:0] ALE /CS /RD,/WR Lower-order address Higher-order address Data Lower-order address Higher-order address Data Dummy cycle Normal cycle Chip selector recovery cycle TMP19A64 (rev1.1) 8-23 TMP19A64C1D 8.5 Bus Arbitration The TMP19A64 can be connected to an external bus master. The arbitration of bus control authority with the external bus master is executed by using the two signals, BUSRQ and BUSAK . The external bus master can acquire control authority for TMP19A64 external buses only, and cannot acquire control authority for internal buses. (1) Accessible range of external bus master The external bus master can acquire control authority for TMP19A64 external buses only, and cannot acquire control authority for internal buses (G-BUS). Therefore, the external bus master cannot access the internal memories or the internal I/O. The arbitration of bus control authority for external buses is executed by the external bus interface circuit (EBIF), and this is independent of the CPU and the internal DMAC. Even when the external bus master holds the external bus control authority, the CPU and the internal DMAC can access the internal ROM, RAM and registers. On the other hand, if the CPU or the internal DMAC tries to access an external memory when the external bus master holds the external bus control authority, the CPU or the internal DMAC has to wait until the external bus master releases the bus. For this reason, if the BUSRQ remains active, the TMP19A64 can lock. (2) Acquisition of bus control authority The external bus master requests the TMP19A64 for bus control authority by asserting the BUSRQ signal. The TMP19A64 samples the BUSRQ signal at the break of external bus cycles on the internal buses (GBUS) and determines whether or not to give the bus control authority to the external bus master. When it gives the bus control authority to the external bus master, it asserts the BUSAK signal. At the same time, it makes address buses, data buses and bus control signals ( RD and WR ) in a state of high impedance. (The internal pull-up is enabled for the R/ W , HWR and CSx .) Depending on the relationship between the size of data to be loaded or stored and the external memory bus width, two or more bus cycles can occur in response to a single data transfer (bus sizing). In this case, the end of the last bus cycle is the break of external bus cycles. If access to external areas occurs consecutively on the TMP19A64, a dummy cycle can be inserted. Again, requests for buses are accepted at the break of external bus cycles on the internal buses (G-BUS). During a dummy cycle, the next external bus cycle is already started on the internal buses. Therefore, even if the BUSRQ signal is asserted during a dummy cycle, the bus is not released until the next external bus cycle is completed. Keep asserting the BUSRQ signal until the bus control authority is released. Fig. 8.5.1 shows the timing of acquiring bus control authority by the external bus master. TMP19A64 (rev1.1) 8-24 TMP19A64C1D tsys Internal address External address BUSRQ BUSAK TMP19A64 external access TMP19A64 external access TMP19A64 external access External bus master cycle TMP19A64 external access BUSRQ is at the "H" level. The TMP19A64 recognizes that the BUSRQ is at the "L" level, and releases the bus at the end of the bus cycle. When the bus is completed, the TMP19A64 asserts BUSAK . The external bus master recognizes that the BUSAK is at the "L" level, and acquires the bus control authority to start bus operations. Fig. 8.5.1 Bus Control Authority Acquisition Timing (3) Release of bus control authority The external bus master releases the bus control authority when it becomes unnecessary. If the external bus master no longer needs the bus control authority that it has held, it deasserts the BUSRQ signal and returns the bus control authority to the TMP19A64. Fig. 8.5.2 shows the timing of releasing unnecessary bus control authority. tsys Internal address External address BUSRQ BUSAK TMP19A64 external access TMP19A64 external access TMP19A64 external access External bus master cycle TMP19A64 external access The external bus master has the bus control authority. The external bus master deasserts the BUSRQ , as it no longer requires the bus control authority. The TMP19A64 recognizes that the BUSRQ is at the "H" level, and deasserts the BUSAK . Fig. 8.5.2 Timing of Releasing Bus Control Authority TMP19A64 (rev1.1) 8-25 TMP19A64C1D 9. The Chip Selector and Wait Controller The TMP19A64 can be connected to external devices (I/O devices, ROM and SRAM). 6-block address spaces (CS0 through CS5) can be established in the TMP19A64 and three parameters can be specified for each 4-block address and other address spaces: data bus width, the number of waits and the number of dummy cycles. CS0 through CS5 (also used as P40 through P45) are the output pins corresponding to spaces CS0 through CS5. These pins generate chip selector signals (for ROM and SRAM) to each space when the CPU designates an address in which spaces CS0 through CS5 are selected. For chip selector signals to be generated, however, the port 4 controller register (P4CR) and the port 4 function register (P4FC) must be set appropriately. The specification of the spaces CS0 through CS5 is to be performed with a combination of base addresses (BAn, n=0 to 5) and mask addresses (MAn, n=0 to 5) using the base and mask address setting registers (BMA0 through BMA5). Meanwhile, master enable, data bus width, the number of waits and the number of dummy cycles for each address space are specified in the chip selector and wait controller registers (B01CS, B23CS, B45CS and BEXCS). A bus wait request pin ( WAIT ) is provided as an input pin to control the status of these settings. 9.1 Specifying Address Spaces Spaces CS0 through CS5 are specified using the base and mask address setting registers (BMA0 through BMA5). In each bus cycle, a comparison is made to see if each address on the bus is located in the space CS0 through CS5. If the result of a comparison is a match, it is considered that the designated CS space has been accessed and chip selector signals are output from pins CS0 through CS5 and the operations specified by the chip selector and wait controller registers (B01CS, B23CS and B45CS) are executed. (Refer to "9.2 The Chip Selector and Wait Controller.") 9.1.1 Base and Mask Address Setting Registers Figures 9.1.1 to 3 show base and mask address setting registers. For base addresses (BA0 through BA5), a start address in the space CS0 through CS5 is specified. In each bus cycle, the chip selector and wait controller compare values in their registers with addresses and those addresses with address bits masked by the mask address (MA0 through MA5) are not compared. The size of an address space is determined by the mask address setting. (1) Base addresses Base address BAn specifies the higher-order 16 bits (A31 through A16) of the start address. The lower-order 16 bits (A15 to A0) of the start address are always set to "0." Therefore, the start address begins with 0x0000_0000H and increases in 64 kilobyte units. Fig. 9.1.4 shows the relationship between the start address and the BAn value. (2) Mask addresses Mask address (MAn) specifies which address bit value is to be compared. The address on the bus that corresponds to the bit for which "0" is written on the address mask MAn is to be included in address comparison to determine if the address is in the area of the CS0 to CS5 spaces. The bit for which "1" is written is not included in address comparison. TMP19A64 (rev1.1) 9-1 TMP19A64C1D CS0 to CS5 spaces have different address bits that can be masked by MA0 to MA5. CS0 space and CS1 space: A29 through A14 CS2 space and CS3 space: A30 through A15 CS4 space and CS5 space: A30 through A15 (Note) Address settings must be made using physical addresses. TMP19A64 (rev1.1) 9-2 TMP19A64C1D Base and mask address setting registers BMA0 (0xFFFF_E400H)-BMA5 (0xFFFF_E414H) 31 BMA0 bit Symbol (0xFFFF_E400H) Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 30 29 28 BA0 R/W 0 23 0 22 0 0 0 0 A31 to A24 to be set as a start address 21 20 BA0 R/W 0 15 0 14 0 0 0 0 A23 to A16 to be set as a start address 13 12 MA0 R/W 0 7 0 6 0 0 Make sure that you write "0." 5 4 MA0 R/W 1 1 1 1 1 1 CS0 space size setting 0: Address for comparison 29 28 BA1 R/W 0 23 bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 0 22 0 0 0 0 A31 to A24 to be set as a start address 21 20 BA1 R/W 0 15 0 14 0 0 0 0 A23 to A16 to be set as a start address 13 12 MA1 R/W 0 7 0 6 0 0 Make sure that you write "0." 5 4 MA1 R/W 1 1 1 1 1 1 CS1 space size setting 0: Address for comparison 1 1 0 3 0 2 1 1 1 0 11 10 0 9 0 8 19 18 0 17 0 16 27 26 1 1 0 3 0 2 1 1 1 0 11 10 0 9 0 8 19 18 0 17 0 16 27 26 25 24 31 BMA1 bit Symbol (0xFFFF_E404H) Read/Write After reset Function 30 25 24 (Note) Make sure that you write "0" for bits 10 through 15 for BMA0 and BMA1. The size of both the CS0 and CS1 spaces can be a minimum of 16 KB to a maximum of 1 GB. The external address space of the TMP19A64 is 16 MB and so bits 10 through 15 must be set to "0" as addresses A24 through A29 are not masked. Fig. 9.1.1 Base and Mask Address Setting Registers (BMA0, BMA1) TMP19A64 (rev1.1) 9-3 TMP19A64C1D 31 BMA2 bit Symbol (0xFFFF_E408H) Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 30 29 28 BA2 R/W 27 26 25 24 0 23 0 22 0 0 0 0 A31 to A24 to be set as a start address 21 20 BA2 R/W 19 18 0 17 0 16 0 15 0 14 0 0 0 0 A23 to A16 to be set as a start address 13 12 MA2 R/W 11 10 0 9 0 8 0 7 0 6 0 0 0 Make sure that you write "0." 5 4 MA2 R/W 3 0 2 0 1 1 0 1 1 1 1 1 1 CS2 space size setting 0: Address for comparison 29 28 BA3 R/W 27 26 1 1 31 BMA3 bit Symbol (0xFFFF_E40CH) Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 30 25 24 0 23 0 22 0 0 0 0 A31 to A24 to be set as a start address 21 20 BA3 R/W 19 18 0 17 0 16 0 15 0 14 0 0 0 0 A23 to A16 to be set as a start address 13 12 MA3 R/W 11 10 0 9 0 8 0 7 0 6 0 0 0 Make sure that you write "0." 5 4 MA3 R/W 3 0 2 0 1 1 0 1 1 1 1 1 1 CS3 space size setting 0: Address for comparison 1 1 (Note) Make sure that you write "0" for bits 9 through 15 for BMA2 and BMA3. The size of both the CS2 and CS3 spaces can be a minimum of 32 KB to a maximum of 2 GB. The external address space of the TMP19A64 is 16 MB and so bits 9 through 15 must be set to "0" as addresses A24 through A30 are not masked. Fig. 9.1.2 Base and Mask Address Setting Registers (BMA2, BMA3) TMP19A64 (rev1.1) 9-4 TMP19A64C1D 31 BMA4 bit Symbol (0xFFFF_E410H) Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 30 29 28 BA4 R/W 27 26 25 24 0 23 0 22 0 0 0 0 A31 to A24 to be set as a start address 21 20 BA4 R/W 19 18 0 17 0 16 0 15 0 14 0 0 0 0 A23 to A16 to be set as a start address 13 12 MA4 R/W 11 10 0 9 0 8 0 7 0 6 0 0 0 Make sure that you write "0." 5 4 MA4 R/W 3 0 2 0 1 1 0 1 1 1 1 1 1 CS4 space size setting 0: Address for comparison 29 28 BA5 R/W 27 26 1 1 31 BMA5 bit Symbol (0xFFFF_E414H) Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 30 25 24 0 23 0 22 0 0 0 0 A31 to A24 to be set as a start address 21 20 BA5 R/W 19 18 0 17 0 16 0 15 0 14 0 0 0 0 A23 to A16 to be set as a start address 13 12 MA5 R/W 11 10 0 9 0 8 0 7 0 6 0 0 0 Make sure that you write "0." 5 4 MA5 R/W 3 0 2 0 1 1 0 1 1 1 1 1 1 CS5 space size setting 0: Address for comparison 1 1 (Note) Make sure that you write "0" for bits 9 through 15 for BMA4 and BMA5. The size of both the CS4 and CS5 spaces can be a minimum of 32 KB to a maximum of 2 GB. The external address space of the TMP19A64 is 16 MB and so bits 9 through 15 must be set to "0" as addresses A24 through A30 are not masked. Fig. 9.1.3 Base and Mask Address Setting Registers (BMA4, BMA5) TMP19A64 (rev1.1) 9-5 TMP19A64C1D Address 0xFFFF_FFFFH Start address Base address value (BAn) FFFFH 0xFFFF_0000H 0x0006_0000H 0x0005_0000H 0x0004_0000H 0x0003_0000H 0x0002_0000H 0x0001_0000H 0x0000_0000H 64 KB 0x0000_0000H 0006H 0005H 0004H 0003H 0002H 0001H 0000H Fig. 9.1.4 Start and Base Address Register Values 9.1.2 * How to Define Start Addresses and Address Spaces To specify a space of 64 KB starting at 0xC000_0000 in the CS0 space, the base and mask address registers must be programmed as shown below. 31 BA0 16 15 MA0 0 11000000000000000000000000000011 C 0 0 0 0 0 0 3 Values to be set in the base and mask address registers (BMA0) In the base address (BA0), specify "0xC000" that corresponds to higher 16 bits of a start address, while in the mask address (MA0), specify whether a comparison of addresses in the space A29 through A16 is to be made or not. To ensure a comparison of A29 through A16, set bits 15 to 2 of the mask address (MA0) to "0." A comparison of addresses of A31 and A30 will definitely be made. This setting allows A31 through A16 to be compared with the value specified as a start address. As A15 through A0 are masked, a space of 64 KB from 0xC000_0000 to 0xC000_FFFF is designated as a CS0 space and the CSO signal is asserted if there is a match with an address on the bus. TMP19A64 (rev1.1) 9-6 TMP19A64C1D * To specify a space of 1 MB starting at 0x1FD0_0000 in the CS2 space, the base and mask address registers must be programmed as shown below. 31 BA2 16 15 MA2 0 00011111110100000000000000011111 1 F D 0 0 0 1 F Values to be set in the base and mask address registers (BMA2) In the base address (BA2), specify "0x1FD0" that corresponds to higher 16 bits of a start address, while in the mask address (MA2), specify whether a comparison of addresses in the space A30 through A15 is to be made or not. To ensure a comparison of A30 through A20, set bits 15 to 5 of the mask address (MA2) to "0." A comparison of A31 will definitely be made. This setting allows A31 through A20 to be compared with the value specified as a start address. As A19 through A0 are masked, a space of 1 MB from 0x1FD0_0000 to 0x1FDF_FFFF is designated as a CS2 space. Note: The CSn signal is not asserted to the following address spaces in the TMP19A64: 0x1FC0_0000 to 0x1FCF_FFFF 0x4000_0000 to 0x400F_FFFF 0xFFFD_6000 to 0xFFFD_FFFF, 0xFFFF_6000 to 0xFFFF_DFFF After a reset, the CS0, CS1, and CS3 through CS5 spaces are disabled, while the whole CS2 space (4 GB) is enabled as an address space. TMP19A64 (rev1.1) 9-7 TMP19A64C1D Table 9.1.1 shows the relationship between CS space and space sizes. If two or more address spaces are specified simultaneously, a space or spaces with a smaller space number will be given priority in space selection. Example: 0xC000_0000 as a start address of the CS0 space with a space size of 16 KB 0xC000_0000 as a start address of the CS1 space with a space size of 64 KB CS0 space CS1 space 0xC000_FFFF 0xC000_3FFF 0xC000_0000 0xC000_3FFF If a space of 0xC000_0000 to 0xC000_0000 0xC000_3FFF is accessed, the CS0 space is selected. Table 9.1.1 CS Space and Space Sizes Size (bytes) 16 K CS space CS0 CS1 CS2 CS3 CS4 CS5 32 K 64 K 128 K 256 K 512 K 1M 2M 4M 8M 16 M TMP19A64 (rev1.1) 9-8 TMP19A64C1D 9.2 The Chip Selector and Wait Controller Fig. 9.2.1 to Fig. 9.2.4 show the chip selector and wait controller registers. For each address space (spaces CS0 through CS5 and other address spaces), each chip selector and wait controller register (B01CS through B45CS, BEXCS) can be programmed to set master enable or disable, to select data bus width, to specify the number of waits and to insert dummy cycles. If two or more address spaces are specified simultaneously, a space or spaces with a smaller space number will be given priority in space selection (order of priority: CS0>CS1>CS2>CS3>CS4>CS5>EXCS). TMP19A64 (rev1.1) 9-9 TMP19A64C1D 7 B01CS (FFFFE480H) bit Symbol Read/Write After reset Function B0OM R/W 6 5 R 0 4 B0BUS R/W 0 Select data bus width. 0: 16bit 1: 8bit 3 2 B0W R/W 1 0 0 0 Select the chip selector output waveform. 00: ROM/RAM Do not make any other settings. 0 1 0 1 Specify the number of waits. (automatic WAIT insertion) 0000: 0WAIT 0001: 1WAIT 0010: 2WAIT 0011: 3WAIT 0100: 4WAIT 0101: 5WAIT 0110: 6WAIT 0111: 7WAIT (external WAIT input) 1010: (2+2N) WAIT 1011: (3+2N) WAIT 1100: (4+2N) WAIT 1101: (5+2N) WAIT 1110: (6+2N) WAIT 1111: (7+2N) WAIT 1000,1001: reserved 11 B0E R/W R 0 10 9 B0RCV R/W 0 0 Specify the number of dummy cycles to be inserted. (read, recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting prohibited 8 15 bit Symbol Read/Write After reset Function R 0 14 B0CSCV R/W 0 Specify the number of dummy cycles to be inserted. (CS0 recovery time) 1: 1 cycle 0: None 22 B1OM R/W 13 B0WCV R/W 0 12 0 Specify the number of dummy cycles to be inserted. (write, recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting prohibited 0 Enable or disable CS0. 0: Disable 1: Enable 23 bit Symbol Read/Write After reset Function 21 R 0 20 B1BUS R/W 0 Select data bus width. 0: 16bit 1: 8bit 19 18 B1W R/W 17 16 0 0 Select the chip selector output waveform. 00: ROM/RAM Do not make any other settings. 0 1 0 1 Specify the number of waits. (automatic WAIT insertion) 0000: 0WAIT 0001: 1WAIT 0010: 2WAIT 0011: 3WAIT 0100: 4WAIT 0101: 5WAIT 0110: 6WAIT 0111: 7WAIT (external WAIT input) 1010: (2+2N) WAIT 1011: (3+2N) WAIT 1100: (4+2N) WAIT 1101: (5+2N) WAIT 1110: (6+2N) WAIT 1111: (7+2N) WAIT 1000,1001: reserved 31 bit Symbol Read/Write After reset Function R 0 30 B1CSCV R/W 0 Specify the number of dummy cycles to be inserted. (CS1 recovery time) 1: 1 cycle 0: None 29 B1WCV R/W 0 0 Specify the number of dummy cycles to be inserted. (write, recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting prohibited 28 27 B1E R/W 0 Enable or disable CS1. 0: Disable 1: Enable R 0 26 25 B1RCV R/W 0 0 Specify the number of dummy cycles to be inserted. (read, recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting prohibited 24 Fig. 9.2.1 Chip Selector and Wait Controller Registers TMP19A64 (rev1.1) 9-10 TMP19A64C1D 7 B23CS bit Symbol (0xFFFF_E484H) Read/Write After reset Function B2OM R/W 6 5 R 0 4 B2BUS R/W 0 Select data bus width. 0: 16bit 1: 8bit 3 2 B2W R/W 1 0 0 0 Select the chip selector output waveform. 00: ROM/RAM Do not make any other settings. 0 1 0 1 Specify the number of waits. (automatic WAIT insertion) 0000: 0WAIT 0001: 1WAIT 0010: 2WAIT 0011: 3WAIT 0100: 4WAIT 0101: 5WAIT 0110: 6WAIT 0111: 7WAIT (external WAIT input) 1010: (2+2N) WAIT 1011: (3+2N) WAIT 1100: (4+2N) WAIT 1101: (5+2N) WAIT 1110: (6+2N) WAIT 1111: (7+2N) WAIT 1000,1001: reserved 11 B2E 1 Enable or disable CS2. 0: Disable 1: Enable 10 B2M 9 B2RCV 8 15 bit Symbol Read/Write After reset Function R 0 14 B2CSCV R/W 0 Specify the number of dummy cycles to be inserted. (CS2 recovery time) 1: 1 cycle 0: None 22 B3OM R/W 13 B2WCV R/W 12 0 0 Specify the number of dummy cycles to be inserted. (write, recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting prohibited R/W 0 0 0 Select CS2 Specify the number of space. dummy cycles to be 0: 4G space inserted. 1: CS space (read, recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting prohibited 23 bit Symbol Read/Write After reset Function 21 R 0 20 B3BUS R/W 0 Select data bus width. 0: 16bit 1: 8bit 19 18 B3W R/W 17 16 0 0 Select the chip select output waveform. 00: ROM/RAM Do not make any other settings. 0 1 0 1 Specify the number of waits. (automatic WAIT insertion) 0000: 0WAIT 0001: 1WAIT 0010: 2WAIT 0011: 3WAIT 0100: 4WAIT 0101: 5WAIT 0110: 6WAIT 0111: 7WAIT (external WAIT input) 1010: (2+2N) WAIT 1011: (3+2N) WAIT 1100: (4+2N) WAIT 1101: (5+2N) WAIT 1110: (6+2N) WAIT 1111: (7+2N) WAIT 1000,1001: reserved 27 B3E R/W 0 Enable or disable CS3. 0: Disable 1: Enable 26 R 0 25 B3RCV R/W 0 0 Specify the number of dummy cycles to be inserted. (read, recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting prohibited 24 31 bit Symbol Read/Write After reset Function R 0 30 B3CSCV R/W 0 Specify the number of dummy cycles to be inserted. (CS3 recovery time) 1: 1 cycle 0: None 29 B3WCV R/W 28 0 0 Specify the number of dummy cycles to be inserted. (write, recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting prohibited Fig. 9.2.2 Chip Selector and Wait Controller Registers TMP19A64 (rev1.1) 9-11 TMP19A64C1D 7 B45CS bit Symbol (0xFFFF_E488H) Read/Write After reset Function B4OM R/W 6 5 R 0 4 B4BUS R/W 0 Select data bus width. 0: 16bit 1: 8bit 3 2 B4W R/W 1 0 0 0 Select the chip selector output waveform. 00: ROM/RAM Do not make any other settings. 0 1 0 1 Specify the number of waits. (automatic WAIT insertion) 0000: 0WAIT 0001: 1WAIT 0010: 2WAIT 0011: 3WAIT 0100: 4WAIT 0101: 5WAIT 0110: 6WAIT 0111: 7WAIT (external WAIT input) 1010: (2+2N) WAIT 1011: (3+2N) WAIT 1100: (4+2N) WAIT 1101: (5+2N) WAIT 1110: (6+2N) WAIT 1111: (7+2N) WAIT 1000,1001: reserved 11 B4E R/W 1 Enable or disable CS4. 0: Disable 1: Enable 10 R 0 9 B4RCV R/W 0 0 Specify the number of dummy cycles to be inserted. (read, recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting prohibited 8 15 bit Symbol Read/Write After reset Function R 0 14 B4CSCV R/W 0 Specify the number of dummy cycles to be inserted. (CS4 recovery time) 1: 1 cycle 0: None 22 B5OM R/W 13 B4WCV R/W 12 0 0 Specify the number of dummy cycles to be inserted. (write, recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting prohibited 23 bit Symbol Read/Write After reset Function 21 R 0 20 B5BUS R/W 0 Select data bus width. 0: 16bit 1: 8bit 19 18 B5W R/W 17 16 0 0 Select the chip select output waveform. 00: ROM/RAM Do not make any other settings. 0 1 0 1 Specify the number of waits. (automatic WAIT insertion) 0000: 0WAIT 0001: 1WAIT 0010: 2WAIT 0011: 3WAIT 0100: 4WAIT 0101: 5WAIT 0110: 6WAIT 0111: 7WAIT (external WAIT input) 1010: (2+2N) WAIT 1011: (3+2N) WAIT 1100: (4+2N) WAIT 1101: (5+2N) WAIT 1110: (6+2N) WAIT 1111: (7+2N) WAIT 1000,1001: reserved 27 B5E R/W 0 Enable or disable CS5. 0: Disable 1: Enable 26 R 0 25 B5RCV R/W 0 0 Specify the number of dummy cycles to be inserted. (read, recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting prohibited 24 31 bit Symbol Read/Write After reset Function R 0 30 B5CSCV R/W 0 Specify the number of dummy cycles to be inserted. (CS5 recovery time) 1: 1 cycle 0: None 29 B5WCV R/W 28 0 0 Specify the number of dummy cycles to be inserted. (write, recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting prohibited Fig. 9.2.3 Chip Selector and Wait Controller Registers TMP19A64 (rev1.1) 9-12 TMP19A64C1D 7 BEXCS bit Symbol (0xFFFF_E48CH) Read/Write After reset Function BEXOM R/W 6 5 R 0 4 BEXBUS R/W 0 Select data bus width. 0: 16bit 1: 8bit 3 2 BEXW R/W 1 0 0 0 Select the chip selector output waveform. 00: ROM/RAM Do not make any other settings. 0 1 0 1 Specify the number of waits. (automatic WAIT insertion) 0000: 0WAIT 0001: 1WAIT 0010: 2WAIT 0011: 3WAIT 0100: 4WAIT 0101: 5WAIT 0110: 6WAIT 0111: 7WAIT (external WAIT input) 1010: (2+2N) WAIT 1011: (3+2N) WAIT 1100: (4+2N) WAIT 1101: (5+2N) WAIT 1110: (6+2N) WAIT 1111: (7+2N) WAIT 1000,1001: reserved 11 R/W 0 10 R 0 9 BEXRCV R/W 0 0 Specify the number of dummy cycles to be inserted. (read, recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting prohibited 18 8 15 bit Symbol Read/Write After reset Function R 0 14 BECSCV R/W 0 Specify the number of dummy cycles to be inserted. 1: 1 cycle 0: None 13 BEXWCV R/W 12 0 0 Specify the number of dummy cycles to be inserted. (write, recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting prohibited 21 R 23 bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 22 20 19 0 31 0 30 R 0 29 0 28 0 27 R/W 0 0 26 0 25 R 0 0 24 0 0 0 0 0 0 Fig. 9.2.4 Chip Selector and Wait Controller Registers A reset of the TMP19A64 allows the port 4 controller register (P4CR) and the port 4 function register (P4FC) to be cleared to "0," and the CS signal output is disabled. To output the CS signals, set the corresponding bits to "1" at the P4FC and the P4CR in that order. The CS recovery time can be configured in any other areas than the CS setting areas, but CS signals will not be output. TMP19A64 (rev1.1) 9-13 TMP19A64C1D 10. DMA Controller (DMAC) The TMP19A64 has a built-in 8-channel DMA Controller (DMAC). 10.1 Features The DMAC of the TMP19A64 has the following features: (1) DMA with 8 independent channels (2) Two types of requests for bus control authority: With and without snoop requests (3) Transfer requests: Internal requests (software initiated)/external requests (external interrupts, interrupt requests given by internal peripheral I/Os, and requests given by the DREQ pin) Requests given by the DREQ pin (CH2, 3): Level mode (memory memory) Edge mode (memory I/O, I/O to memory) (4) Transfer mode: Dual address mode (5) Transfer devices: Memory-to-memory, memory-to-I/O, I/O-to-memory (6) Device size: 32-bit memory (8 or 16 bits can be specified using the CS/WAIT controller); I/O of 8, 16 or 32 bits (7) Address changes: Increase, decrease, fixed, irregular increase, irregular decrease (8) Channel priority: Fixed (in ascending order of channel numbers) (9) Endian switchover function TMP19A64(rev1.1)-10-1 TMP19A64C1D 10.2 Configuration 10.2.1 Internal Connections of the TMP19A64 Fig. 10.2.1 shows the internal connections with the DMAC in the TMP19A64. DREQ [3 : 2] DACK [3 : 2] Port F and J function control DACK [7 : 0]* Interrupt controller TX19A processor core INTDREQ [7 : 0]* (external request) External interrupt request Internal I/O interrupt request Notification to release bus control authority DMAC BUSGNT * Request for bus control authority Request to release bus control authority Notification of bus control authority ownership Control Address Data BUSREQ * BUSREL * HAVEIT * (Note) In Fig. 10.1, signals indicated by * are internal signals. Fig. 10.2.1 DMAC Connections in the TMP19A64 The DMAC has eight DMA channels. Each of these channels handles the data transfer request signal (INTDREQn) from the interrupt controller and the acknowledgment signal (DACKn) generated in response to INTDREQn, where "n" is a channel number from 0 to 7. External pins (DREQ2 and DREQ3) are internally wired to allow them to function as pins of the port F and J. To use them as pins of the port F and J, they must be selected by setting the function control register PFFC and PJFC to an appropriate setting. If both ports are set to use the DMAC function, the port F is given priority in using the DMAC function. Pins, DACK2 and DACK3, handle the data transfer request and acknowledge signal output supplied through external pins, DREQ2 and DREQ3. Channel 0 is given higher priority than channel 1, channel 1 higher priority than channel 2 and channel 2 higher priority than channel 3. Subsequent channels are given priority in the same manner. The TX19A processor core has a snoop function. Using the snoop function, the TX19A processor core opens the core's data bus to the DMAC, thus allowing the DMAC to access the internal ROM and RAM linked to the core. The DMAC is capable of determining whether or not to use this snoop function. For further information on the snoop function, refer to 10.2.3 "Snoop Function." Two types of bus control authority (SREQ and GREQ) are available to the DMAC and which type of control right to use depends on the use or nonuse of the snoop function. GREQ is a request for bus control authority if the DMAC does not use the snoop function, while SREQ is a request for bus control authority if the DMAC uses the snoop function. SREQ is given higher priority than GREQ. TMP19A64(rev1.1)-10-2 TMP19A64C1D 10.2.2 DMAC Internal Blocks Fig. 10.2.2 shows the internal blocks of the DMAC. Channel 7 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 0 31 Source address register (SARx) Destination address register (DARx) Byte count register (BSRx) Channel control register (CCRx) Channel status register (CSRx) DMA transfer control register (DTCRx) (x0 through 7) DMA control register (DCR) Request select register (RSR) Data holding register (DHR) 0 Fig. 10.2.2 DMAC Internal Blocks 10.2.3 Snoop Function The TX19A processor core has a snoop function. If the snoop function is activated, the TX19A processor core opens the core's data bus to the DMAC and suspends its own operation until the DMAC withdraws a request for bus control authority. If the snoop function is enabled, the DMAC can access the internal RAM and ROM and therefore designate the RAM or ROM as a source or destination. If the snoop function is not used, the DMAC cannot access the internal RAM or ROM. However, the G-Bus is opened to the DMAC. If the TX19A processor core attempts to access memory or the I/O by way of the G-Bus and if the DMAC does not accept a bus control release request, bus operations cannot be executed and, as a result, the pipeline stalls. (Note) If the snoop function is not used, the TX19A processor core does not open the data bus to the DMAC. If the data bus is closed and the internal RAM or ROM is designated as a DMAC source or destination, an acknowledgment signal will not be returned in response to a DMAC transfer bus cycle and, as a result, the bus will lock. TMP19A64(rev1.1)-10-3 TMP19A64C1D 10.3 Registers The DMAC has fifty-one 32-bit registers. Table 10.3.1 shows the register map of the DMAC. Table 10.3.1 DMAC Registers Address 0xFFFF_E200 0xFFFF_E204 0xFFFF_E208 0xFFFF_E20C 0xFFFF_E210 0xFFFF_E218 0xFFFF_E220 0xFFFF_E224 0xFFFF_E228 0xFFFF_E22C 0xFFFF_E230 0xFFFF_E238 0xFFFF_E240 0xFFFF_E244 0xFFFF_E248 0xFFFF_E24C 0xFFFF_E250 0xFFFF_E258 0xFFFF_E260 0xFFFF_E264 0xFFFF_E268 0xFFFF_E26C 0xFFFF_E270 0xFFFF_E278 0xFFFF_E280 0xFFFF_E284 0xFFFF_E288 0xFFFF_E28C 0xFFFF_E290 0xFFFF_E298 0xFFFF_E2A0 0xFFFF_E2A4 0xFFFF_E2A8 0xFFFF_E2AC 0xFFFF_E2B0 0xFFFF_E2B8 0xFFFF_E2C0 0xFFFF_E2C4 0xFFFF_E2C8 0xFFFF_E2CC 0xFFFF_E2D0 0xFFFF_E2D8 Register symbol CCR0 CSR0 SAR0 DAR0 BCR0 DTCR0 CCR1 CSR1 SAR1 DAR1 BCR1 DTCR1 CCR2 CSR2 SAR2 DAR2 BCR2 DTCR2 CCR3 CSR3 SAR3 DAR3 BCR3 DTCR3 CCR4 CSR4 SAR4 DAR4 BCR4 DTCR4 CCR5 CSR5 SAR5 DAR5 BCR5 DTCR5 CCR6 CSR6 SAR6 DAR6 BCR6 DTCR6 Register name Channel control register (ch. 0) Channel status register (ch. 0) Source address register (ch. 0) Destination address register (ch. 0) Byte count register (ch. 0) DMA transfer control register (ch. 0) Channel control register (ch. 1) Channel status register (ch. 1) Source address register (ch. 1) Destination address register (ch. 1) Byte count register (ch. 1) DMA transfer control register (ch. 1) Channel control register (ch. 2) Channel status register (ch. 2) Source address register (ch. 2) Destination address register (ch. 2) Byte count register (ch. 2) DMA transfer control register (ch. 2) Channel control register (ch. 3) Channel status register (ch. 3) Source address register (ch. 3) Destination address register (ch. 3) Byte count register (ch. 3) DMA transfer control register (ch. 3) Channel control register (ch. 4) Channel status register (ch. 4) Source address register (ch. 4) Destination address register (ch. 4) Byte count register (ch. 4) DMA transfer control register (ch. 4) Channel control register (ch. 5) Channel status register (ch. 5) Source address register (ch. 5) Destination address register (ch. 5) Byte count register (ch. 5) DMA transfer control register (ch. 5) Channel control register (ch. 6) Channel status register (ch. 6) Source address register (ch. 6) Destination address register (ch. 6) Byte count register (ch. 6) DMA transfer control register (ch. 6) TMP19A64(rev1.1)-10-4 TMP19A64C1D Table 10.3.1 DMAC Registers (2) 0xFFFF_E2E0 0xFFFF_E2E4 0xFFFF_E2E8 0xFFFF_E2EC 0xFFFF_E2F0 0xFFFF_E2F8 0xFFFF_E300 0xFFFF_E304 0xFFFF_E30C CCR7 CSR7 SAR7 DAR7 BCR7 DTCR7 DCR RSR DHR Channel control register (ch. 7) Channel status register (ch. 7) Source address register (ch. 7) Destination address register (ch. 7) Byte count register (ch. 7) DMA transfer control register (ch. 7) DMA control register (DMAC) Request select register (DMAC) Data holding register (DMAC) TMP19A64(rev1.1)-10-5 TMP19A64C1D 10.3.1 DMA Control Register (DCR) 7 6 Rst6 0 14 5 Rst5 0 13 4 Rst4 3 Rst3 2 Rst2 0 10 1 Rst1 0 9 0 Rst0 0 8 DCR bit Symbol (0xFFFF_E300H) Read/Write After reset Function Rst7 0 15 W 0 0 See detailed description. 12 11 R 0 bit Symbol Read/Write After reset Function 23 bit Symbol Read/Write After reset Function 31 30 29 28 22 21 20 19 R 0 27 R 0 18 17 16 26 25 24 bit Symbol Read/Write After reset Function Rstall W 0 See detailed description. Bit 31 Mnemonic Rstall Field name Reset all Description Performs a software reset of the DMAC. If the Rstall bit is set to 1, the values of all the internal registers of the DMAC are reset to their initial values. All transfer requests are canceled and all eight channels go into an idle state. 0: Don't care 1: Initializes the DMAC Performs a software reset of the DMAC channel 7. If the Rst7 bit is set to 1, internal registers of the DMAC channel 7 and a corresponding bit of the channel 7 of the RSR register are reset to their initial values. The transfer request of the channel 7 is canceled and the channel 7 goes into an idle state. 0: Don't care 1: Initializes the DMAC channel 7 Performs a software reset of the DMAC channel 6. If the Rst6 bit is set to 1, internal registers of the DMAC channel 6 and a corresponding bit of the channel 6 of the RSR register are reset to their initial values. The transfer request of the channel 6 is canceled and the channel 6 goes into an idle state. 0: Don't care 1: Initializes the DMAC channel 6 Performs a software reset of the DMAC channel 5. If the Rst5 bit is set to 1, internal registers of the DMAC channel 5 and a corresponding bit of the channel 5 of the RSR register are reset to their initial values. The transfer request of the channel 5 is canceled and the channel 5 goes into an idle state. 0: Don't care 1: Initializes the DMAC channel 5 7 Rst7 Reset 7 6 Rst6 Reset 6 5 Rst5 Reset 5 Fig. 10.3.1 DMA Control Register (DCR) (1 of 2) TMP19A64(rev1.1)-10-6 TMP19A64C1D Bit 4 Mnemonic Rst4 Field name Reset 4 Description Performs a software reset of the DMAC channel 4. If the Rst4 bit is set to 1, internal registers of the DMAC channel 4 and a corresponding bit of the channel 4 of the RSR register are reset to their initial values. The transfer request of the channel 4 is canceled and the channel 4 goes into an idle state. 0: Don't care 1: Initializes the DMAC channel 4 Performs a software reset of the DMAC channel 3. If the Rst3 bit is set to 1, internal registers of the DMAC channel 3 and a corresponding bit of the channel 3 of the RSR register are reset to their initial values. The transfer request of the channel 3 is canceled and the channel 3 goes into an idle state. 0: Don't care 1: Initializes the DMAC channel 3 Performs a software reset of the DMAC channel 2. If the Rst2 bit is set to 1, internal registers of the DMAC channel 2 and a corresponding bit of the channel 2 of the RSR register are reset to their initial values. The transfer request of the channel 2 is canceled and the channel 2 goes into an idle state. 0: Don't care 1: Initializes the DMAC channel 2 Performs a software reset of the DMAC channel 1. If the Rst1 bit is set to 1, internal registers of the DMAC channel 1 and a corresponding bit of the channel 1 of the RSR register are reset to their initial values. The transfer request of the channel 1 is canceled and the channel 1 goes into an idle state. 0: Don't care 1: Initializes the DMAC channel 1 Performs a software reset of the DMAC channel 0. If the Rst0 bit is set to 1, internal registers of the DMAC channel 0 and a corresponding bit of the channel 0 of the RSR register are reset to their initial values. The transfer request of the channel 0 is canceled and the channel 0 goes into an idle state. 0: Don't care 1: Initializes the DMAC channel 0 3 Rst3 Reset 3 2 Rst2 Reset 2 1 Rst1 Reset 1 0 Rst0 Reset 0 Fig. 10.3.1 DMA Control Register (DCR) (2 of 2) (Note 1) If a write to the DCR register occurs during a software reset right after the last round of DMA transfer is completed, the interrupt to stop DMA transfer is not canceled although the channel register is initialized. (Note 2) An attempt to execute a write (software reset) to the DCR register by DMA transfer must be strictly avoided. TMP19A64(rev1.1)-10-7 TMP19A64C1D 10.3.2 Channel Control Registers (CCRn) (n=0 through 7) 7 SAC R/W 0 15 bit Symbol Read/Write After reset Function W 0 Always set this bit to "0." 23 NIEn R/W 1 See detailed description. 31 Str W 0 See detailed description. CCRn (0xFFFF_E200H) (0xFFFF_E220H) (0xFFFF_E240H) (0xFFFF_E260H) (0xFFFF_E280H) (0xFFFF_E2A0H) (0xFFFF_E2C0H) (0xFFFF_E2E0H) bit Symbol Read/Write After reset Function 6 DIO R/W 0 14 ExR R/W 0 5 DAC R/W 0 13 PosE R/W 0 4 3 TrSiz R/W 2 1 DPS R/W 0 9 SIO R/W 0 0 0 0 0 See detailed description. 12 11 10 Lev SReq RelEn R/W R/W R/W 0 0 0 See detailed description. 0 8 SAC R/W 0 bit Symbol Read/Write After reset Function 22 AblEn R/W 1 21 R/W 1 20 19 18 R/W 0 R/W R/W 0 0 Always set this bit to "0." 30 29 28 27 26 W 0 See Always set detailed this bit to description. "0." 25 24 W 0 Always set this bit to "0." 17 Big R/W 1 16 bit Symbol Read/Write After reset Function 0 0 0 0 0 0 Bit 31 Mnemonic Str Field name Channel start Description Start (initial value: 0) Starts channel operation. If this bit is set to 1, the channel goes into a standby mode and starts to transfer data in response to a transfer request. Only a write of 1 is valid to the Str bit and a write of 0 is ignored. A read always returns a 0. 1: Starts channel operation This is a reserved bit. Always set this bit to "0." Normal Completion Interrupt Enable (initial value: 1) 1: Normal completion interrupt enable 0: Normal completion interrupt disable Abnormal Completion Interrupt Enable (initial value: 1) 1: Abnormal completion interrupt enable 0: Abnormal completion interrupt disable This is a reserved bit. Although its initial value is "1," always set this bit to "0." This is a reserved bit. Always set this bit to "0." This is a reserved bit. Always set this bit to "0." This is a reserved bit. Always set this bit to "0." 24 23 NIEn (Reserved) Normal completion interrupt enable Abnormal completion interrupt enable (Reserved) (Reserved) (Reserved) (Reserved) 22 AbIEn 21 20 19 18 Fig. 10.3.2 Channel Control Register (CCRn) (1 of 3) TMP19A64(rev1.1)-10-8 TMP19A64C1D Bit 17 Mnemonic Big Field name Big-endian Description Big Endian (initial value: 1) 1: A channel operates by big-endian 0: A channel operates by little-endian This is a reserved bit. Always set this bit to "0." This is a reserved bit. Always set this bit to "0." 16 15 14 ExR (Reserved) (Reserved) 13 PosE 12 Lev 11 SReq 10 RelEn 9 SIO External request mode External Request Mode (initial value: 0) Selects a transfer request mode. 1: External transfer request (interrupt request or external DREQn request) 0: Internal transfer request (software initiated) Positive edge Positive Edge (initial value: 0) The effective level of the transfer request signal INTDREQn or DREQn is specified. This function is valid only if the transfer request is an external transfer request (if the ExR bit is 1). If it is an internal transfer request (if the ExR bit is 0), the PosE value is ignored. Because the INTDREQn and DREQn signals are active at "L" level, make sure that this PosE bit is set to "0." 1: Setting prohibited 0: The falling edge of the INTDREQn or DREQn signal or the "L" level is effective. The DACKn is active at "L" level. Level mode Level Mode (initial value: 0) Specifies which is used to recognize the external transfer request, signal level or signal change. This setting is valid only if a transfer request is the external transfer request (if the ExR bit is 1). If the internal transfer request is specified as a transfer request (if the ExR bit is 0), the value of the Lev bit is ignored. Because the INTDREQn signal is active at "L" level, make sure that you set the Lev bit to "1." The state of active DREQn is determined by the Lev bit setting. 1: Level mode The level of the DREQn signal is recognized as a data transfer request. (The "L" level is recognized if the PosE bit is 0. 0: Edge mode A change in the DREQn signal is recognized as a data transfer request. (A falling edge is recognized if the PosE bit is 0.) Snoop request Snoop Request (initial value: 0) The use of the snoop function is specified by asserting the bus control request mode. If the snoop function is used, the snoop function of the TX19A processor core is enabled and the DMAC can use the data bus of the TX19A processor core. If the snoop function is not used, the snoop function of the TX19A processor core does not work. 1: Use snoop function (SREQ) 0: Do not use snoop function (GREQ) Release Request Enable (initial value: 0) Bus control release request enable Acknowledgment of the bus control release request made by the TX19A processor core is specified. This function is valid only if GREQ is generated. If SREQ is generated, the TX19A processor core cannot make a bus control release request and, therefore, this function cannot be used. 1: The bus control release request is acknowledged if the DMAC has control of the bus. If the TX19A processor core issues a bus control release request, the DMAC relinquishes control of the bus to the TX19A processor core during a pause in bus operation. 0: The bus control release request is not acknowledged. Source I/O Source Type: I/O (initial value: 0) Specifies the source device. 1: I/O device 0: Memory Fig. 10.3.2 Channel Control Register (CCRn) (2/3) TMP19A64(rev1.1)-10-9 TMP19A64C1D Bit 8:7 Mnemonic SAC Field name Source address count Description Source Address Count (initial value: 00) Source Address Count (initial value: 00) Specifies the manner of change in a source address. 1x: Address fixed 01: Address decrease 00: Address increase Destination Type: I/O (initial value: 0) Specifies a destination device. 1: I/O device 0: Memory Destination Address Count (initial value: 00) Specifies the manner of change in a destination address. 1x: Address fixed 01: Address decrease 00: Address increase Transfer Size (initial value: 00) Specifies the amount of data to be transferred in response to one transfer request. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) Device Port Size (initial value: 00) Specifies the bus width of an I/O device designated as a source or destination device. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) 6 DIO Destination I/O 5:4 DAC Destination address count 3:2 TrSiz Transfer unit 1:0 DPS Device port size Fig. 10.3.2 Channel Control Register (CCRn) (3/3) (Note 1) The CCRn register setting must be completed before the DMAC is put into a standby mode. (Note 2) When accessing the internal I/O or transferring data by DMA in response to the DREQ pin request, make sure that you set the transfer unit TMP19A64(rev1.1)-10-10 TMP19A64C1D 10.3.3 Request Select Register (RSR) 7 6 5 4 R/W 0 3 ReqS3 R/W 0 2 ReqS2 R/W 0 1 0 RSR (0xFFFF_E304H) bit Symbol Read/Write After reset Function R/W 0 R/W R/W 0 0 Always set this bit to "0." 14 13 See detailed description. 15 bit Symbol Read/Write After reset Function 23 bit Symbol Read/Write After reset Function 31 bit Symbol Read/Write After reset Function 12 R 0 11 10 R/W R/W 0 0 Always set this bit to "0." 9 8 22 21 20 R 0 19 18 17 16 30 29 28 R 0 27 26 25 24 Bit 3 Mnemonic ReqS3 Field name Request select (ch.3) Description Request Select (initial value: 0) Selects a source of the external transfer request for the DMA channel 3. 1: Request made by DREQ3 0: Request made by the interrupt controller (INTC) Request Select (initial value: 0) Selects a source of the external transfer request for the DMA channel 2. 1: Request made by DREQ2 0: Request made by the interrupt controller (INTC) 2 ReqS2 Request select (ch.2) Fig. 10.3.3 DMA Control Register (RSR) (Note) Make sure that you write "0" to bits 0, 1 and 4 through 7 of the RSR register. TMP19A64(rev1.1)-10-11 TMP19A64C1D 10.3.4 Channel Status Registers (CSRn) (n=0 through 7) 7 6 5 R 0 15 bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 23 NC R/W 0 22 AbC R/W 0 21 14 13 12 R 0 20 19 18 BES BED Conf R R R 0 0 0 See detailed description. 17 R 0 16 11 4 3 2 1 0 CSRn (0xFFFF_E204H) (0xFFFF_E224H) (0xFFFF_E244H) (0xFFFF_E264H) (0xFFFF_E284H) (0xFFFF_E2A4H) (0xFFFF_E2C4H) (0xFFFF_E2E4H) bit Symbol Read/Write After reset Function R/W R/W R/W 0 0 0 Always set this bit to "0." 10 9 8 bit Symbol Read/Write After reset Function R/W 0 See detailed description. Always set this bit to "0." 31 30 29 Act R 0 See detailed description. 28 27 R 0 26 25 24 Bit 31 Mnemonic Act Field name Channel active Description Channel Active (initial value: 0) Indicates whether the channel is in a standby mode: 1: In a standby mode 0: Not in a standby mode Normal Completion (initial value: 0) Indicates normal completion of channel operation. If an interrupt at normal completion is permitted by the CCR register, the DMAC requests an interrupt when the NC bit becomes 1. This setting can be cleared by writing 0 to the NC bit. If a request for an interrupt at normal completion was previously issued, the request is canceled if the NC bit becomes 0. If an attempt is made to set the Str bit to 1 when the NC bit is 1, an error occurs. To start the next transfer, the NC bit must be cleared to 0. A write of 1 will be ignored. 1: Channel operation has been completed normally. 0: Channel operation has not been completed normally 23 NC Normal completion Fig. 10.3.4 Channel Status Registers (CSRn) (1/2) TMP19A64(rev1.1)-10-12 TMP19A64C1D Bit 22 Mnemonic AbC Field name Abnormal completion Description Abnormal Completion (initial value: 0) Indicates abnormal completion of channel operation. If an interrupt at abnormal completion is permitted by the CCR register, the DMAC requests an interrupt when the AbC bit becomes 1. This setting can be cleared by writing 0 to the AbC bit. If a request for an interrupt at abnormal completion was previously issued, the request is canceled if the AbC bit becomes 0. Additionally, if the AbC bit is cleared to 0, each of the BES, BED and Conf bits are cleared to 0. If an attempt is made to set the Str bit to 1 when the AbC bit is 1, an error occurs. To start the next transfer, the AbC bit must be cleared to 0. A write of 1 will be ignored. 1: Channel operation has been completed abnormally. 0: Channel operation has not been completed abnormally. This is a reserved bit. Always set this bit to "0." Source Bus Error (initial value: 0) 1: A bus error has occurred when the source was accessed. 0: A bus error has not occurred when the source was accessed. Destination Bus Error (initial value: 0) 1: A bus error has occurred when the destination was accessed. 0: A bus error has not occurred when the destination was accessed. Configuration Error (initial value: 0) 1: A configuration error has occurred. 0: A configuration error has not occurred. These three bits are reserved bits. Always set them to "0." 21 20 BES (Reserved) Source bus error 19 BED Destination bus error 18 Conf Configuration error 2:0 (Reserved) Fig. 10.3.4 Channel Status Registers (CSRn) (2/2) TMP19A64(rev1.1)-10-13 TMP19A64C1D 10.3.5 Source Address Registers (SARn) (n=0 through 7) 7 SAddr7 6 SAddr6 5 SAddr5 4 SAddr4 3 SAddr3 2 SAddr2 1 SAddr1 0 SAddr0 SARn (0xFFFF_E208H) (0xFFFF_E228H) (0xFFFF_E248H) (0xFFFF_E268H) (0xFFFF_E288H) (0xFFFF_E2A8H) (0xFFFF_E2C8H) (0xFFFF_E2E8H) bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 15 SAddr15 14 SAddr14 13 SAddr13 23 SAddr23 22 SAddr22 21 SAddr21 31 SAddr31 30 SAddr30 29 SAddr29 R/W 0 See detailed description. 12 11 SAddr12 SAddr11 R/W 0 See detailed description. 20 19 SAddr20 SAddr19 R/W 0 See detailed description. 28 27 SAddr28 SAddr27 R/W 0 See detailed description. 10 SAddr10 9 SAddr9 8 SAddr8 18 SAddr18 17 SAddr17 16 SAddr16 26 SAddr26 25 SAddr25 24 SAddr24 Bit 31 : 0 Mnemonic SAddr Field name Source address Description Source Address (initial value: 0) Specifies the address of the source from which data is transferred using a physical address. This address changes according to the SAC and TrSiz settings of CCRn and the SACM setting of DTCRn. Fig. 10.3.5 Source Address Register (SARn) TMP19A64(rev1.1)-10-14 TMP19A64C1D 10.3.6 Destination Address Register (DARn) (n=0 through 7) 7 DAddr7 6 DAddr6 4 3 DAddr4 DAddr3 R/W 0 See detailed description. 13 12 11 DAddr13 DAddr12 DAddr11 R/W 0 See detailed description. 21 20 19 DAddr21 DAddr20 DAddr19 R/W 0 See detailed description. 29 28 27 DAddr29 DAddr28 DAddr27 R/W 0 See detailed description. 5 DAddr5 2 DAddr2 1 DAddr1 0 DAddr0 DARn (0xFFFF_E20CH) (0xFFFF_E22CH) (0xFFFF_E24CH) (0xFFFF_E26CH) (0xFFFF_E28CH) (0xFFFF_E2ACH) (0xFFFF_E2CCH) (0xFFFF_E2ECH) bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 15 DAddr15 14 DAddr14 10 DAddr10 9 DAddr9 8 DAddr8 23 DAddr23 22 DAddr22 18 DAddr18 17 DAddr17 16 DAddr16 31 DAddr31 30 DAddr30 26 DAddr26 25 DAddr25 24 DAddr24 Bit 31 : 0 Mnemonic DAddr Field name Destination address Description Destination Address (initial value: 0) Specifies the address of the destination to which data is transferred using a physical address. This address changes according to the DAC and TrSiz settings of CCRn and the DACM setting of DTCRn. Fig. 10.3.6 Destination Address Register (DARn) TMP19A64(rev1.1)-10-15 TMP19A64C1D 10.3.7 Byte Count Registers (BCRn) (n=0 through 7) 7 BC7 6 BC6 5 BC5 4 BC4 3 BC3 2 BC2 1 BC1 0 BC0 BCRn (0xFFFF_E210H) (0xFFFF_E230H) (0xFFFF_E250H) (0xFFFF_E270H) (0xFFFF_E290H) (0xFFFF_E2B0H) (0xFFFF_E2D0H) (0xFFFF_E2F0H) bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 15 BC15 14 BC14 13 BC13 23 BC23 22 BC22 21 BC21 31 30 29 R/W 0 See detailed description. 12 11 BC12 BC11 R/W 0 See detailed description. 20 19 BC20 BC19 R/W 0 See detailed description. 28 27 R 0 10 BC10 9 BC9 8 BC8 18 BC18 17 BC17 16 BC16 26 25 24 Bit 23 : 0 Mnemonic BC Field name Byte count Description Byte Count (initial value: 0) Specifies the number of bytes of data to be transferred. The address decreases by the number of pieces of data transferred (a value specified by TrSiz of CCRn). Fig. 10.3.7 Byte Count Register (BCRn) TMP19A64(rev1.1)-10-16 TMP19A64C1D 10.3.8 DMA Transfer Control Register (DTCRn) (n=0 through 7) 7 6 R 0 15 bit Symbol Read/Write After reset Function 23 bit Symbol Read/Write After reset Function 31 bit Symbol Read/Write After reset Function 30 29 28 R 0 22 21 20 R 0 27 26 25 24 14 4 3 DACM R/W 0 0 0 See detailed description. 13 12 11 R 0 19 18 17 16 5 1 0 SACM R/W 0 0 0 See detailed description. 10 9 8 2 DTCRn (0xFFFF_E218H) (0xFFFF_E238H) (0xFFFF_E258H) (0xFFFF_E278H) (0xFFFF_E298H) (0xFFFF_E2B8H) (0xFFFF_E2D8H) (0xFFFF_E2F8H) bit Symbol Read/Write After reset Function Bit 5:3 Mnemonic DACM Field name Destination address count mode Description Destination Address Count Mode Specifies the count mode of the destination address. 000: Counting begins from bit 0 001: Counting begins from bit 4 010: Counting begins from bit 8 011: Counting begins from bit 12 100: Counting begins from bit 16 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited Source Address Count Mode Specifies the count mode of the source address. 000: Counting begins from bit 0 001: Counting begins from bit 4 010: Counting begins from bit 8 011: Counting begins from bit 12 100: Counting begins from bit 16 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited 2:0 SACM Source address count mode Fig. 10.3.8 DMA Transfer Control Register (DTCRn) TMP19A64(rev1.1)-10-17 TMP19A64C1D 10.3.9 Data Holding Register (DHR) 7 DOT7 6 DOT6 5 DOT5 4 DOT4 3 DOT3 2 DOT2 1 DOT1 0 DOT0 DHR bit Symbol (0xFFFF_E30CH) Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 15 DOT15 14 DOT14 13 DOT13 23 DOT23 22 DOT22 21 DOT21 31 DOT31 30 DOT30 29 DOT29 R/W 0 See detailed description. 12 11 DOT12 DOT11 R/W 0 See detailed description. 20 19 DOT20 DOT19 R/W 0 See detailed description. 28 27 DOT28 DOT27 R/W 0 See detailed description. 10 DOT10 9 DOT9 8 DOT8 18 DOT18 17 DOT17 16 DOT16 26 DOT26 25 DOT25 24 DOT24 Bit 31 : 0 Mnemonic DOT Field name Data on transfer Description Data on Transfer (initial value: 0) Data that is read from the source in a dual-address data transfer mode. Fig. 10.3.9 Data Holding Register (DHR) TMP19A64(rev1.1)-10-18 TMP19A64C1D 10.4 Functions 10.4.1 Overview The DMAC is a 32-bit DMA controller capable of transferring data in a system using the TX19A processor core at high speeds without routing data via the core. (1) Source and destination The DMAC handles data transfers from memory to memory and between memory and an I/O device. A device from which data is transferred is called a source device and a device to which data is transferred is called a destination device. Both memory and I/O devices can be designated as a source or destination device. The DMAC supports data transfers from memory to I/O devices, from I/O devices to memory, and from memory to memory, but not between I/O devices. The differences between memory and I/O devices are in the way they are accessed. When accessing an I/O device, the DMAC asserts a DACKn signal. Because there is only one line per channel that carries a DACKn signal, the number of I/O devices accessible during data transfer is limited to one. Therefore, data cannot be transferred between I/O devices. An interrupt factor can be attached to a transfer request to be sent to the DMAC. If an interrupt factor is generated, the interrupt controller (INTC) issues a request to the DMAC (the TX19A processor core is not notified of the interrupt request. For details, see description on Interrupts.). The request issued by the INTC is cleared by the DACKn signal. Therefore, if an I/O device is designated as a device to which data is to be transferred, a request made to the DMAC is cleared after completion of the data transfer (transfer of the amount of data specified by TrSiz). On the other hand, during memory-to-memory transfers, the DACKn signal is asserted only when the number of bytes transferred (value set in the BCRn register) becomes "0." Therefore, one transfer request allows data to be transferred successively without a pause. For example, if data is transferred between a internal I/O and the internal (external) memory of the TMP19A64, a request made by the internal I/O to the DMAC is cleared after completion of each data transfer and the transfer operation is always put in a standby mode for the next transfer request if the number of bytes transferred (value set in the BCRn register) does not become "0." Therefore, the DMA transfer operation continues until the value of the BCRn register becomes "0." (2) Bus control arbitration (bus arbitration) In response to a transfer request made inside the DMAC, the DMAC requests the TX19A processor core to arbitrate bus control authority. When a response signal is returned from the core, the DMAC acquires bus control authority and executes a data transfer bus cycle. In acquiring bus control for the DMAC, use or nonuse of the data bus of the TX19A processor core can be specified; specifically either snoop mode or non-snoop mode can be specified for each channel by using bit 11 (SReq) of the CCRn register. There are cases in which the TX19A processor core requests the release of bus control authority. Whether or not to respond to this request can be specified for each channel by using the bit 10 (RelEn) of the CCRn register. However, this function can only be used in non-snoop mode (GREQ). In snoop mode (SREQ), the TX19A processor core cannot request the release of bus control and, therefore, this function cannot be used. When there are no more transfer requests, the DMAC releases control of the bus. TMP19A64(rev1.1)-10-19 TMP19A64C1D (Note 1) When the DMAC is acquiring bus control authority, NMI is put on hold. (Note 2) Do not bring the TX19A to a halt when the DMAC is in operation. (Note 3) To put the TX19A into IDLE (doze) mode when the snoop function is being used, you must first stop the DMAC. TMP19A64(rev1.1)-10-20 TMP19A64C1D (3) Transfer request modes Two transfer request modes are used for the DMAC: an internal transfer request mode and an external transfer request mode. In the internal transfer request mode, a transfer request is generated inside the DMAC. Setting a start bit (Str bit of the channel control register CCRn) in the internal register of the DMAC to "1" generates a transfer request, and the DMAC starts to transfer data. In the external transfer request mode, after a start bit is set to "1," a transfer request is generated when a transfer request signal INTDREQn output by the INTC is input, or when a transfer request signal DREQn output by an external device is input. For the DMAC, two modes are provided: the level mode in which a transfer request is generated when the "L" level of the INTDREQn signal is detected and a mode in which a transfer request is generated when the falling edge or "L" level of the DREQn signal is detected. (4) Address mode For the DMAC of the TMP19A64, only one address mode is provided: a dual address mode. A single address mode is not available. In the dual address mode, data can be transferred from memory to memory and between memory and an I/O device. Source and destination device addresses are output by the DMAC. To access an I/O device, the DMAC asserts the DACKn signal. In the dual address mode, two bus operations, a read and a write, are executed. Data that is read from a source device for transfer is first put into the data holding register (DHR) inside the DMAC and then written to a destination device. (5) Channel operation The DMAC has eight channels (channels 0 through 7). A channel is activated and put into a standby mode by setting a start (Str) bit in the channel control register (CCRn) to "1." If a transfer request is generated when a channel is in a standby mode, the DMAC acquires bus control authority and transfers data. If there is no transfer request, the DMAC releases bus control authority and goes into a standby mode. If data transfer has been completed, a channel is put in an idle state. Data transfer is completed either normally or abnormally (e.g. occurrence of errors). An interrupt signal can be generated upon completion of data transfer. Fig. 10.4.1 shows the state transitions of channel operation. Bus control authority not acquired Wait Start Bus control authority not acquired Idle Transfer completed Bus control authority acquired Transfer Bus control authority acquired Fig. 10.4.1 Channel Operation State Transition TMP19A64(rev1.1)-10-21 TMP19A64C1D (6) Combinations of transfer modes The DMAC can transfer data by combining each transfer mode as follows: Transfer request Internal External Edge/level "L" level (INTDREQn) "L" level (DREQn) Falling edge (DREQn) Address mode Transfer devices Memory memory Memory memory Memory I/O I/O memory Memory memory Memory I/O I/O memory Dual External (7) Address changes Address changes are broadly classified into three types: increases, decreases and fixed. The type of address change can be specified for each source and destination address by using SAC and DAC in the CCRn register. For a memory device, an increase, decrease or fixed can be specified. For an I/O device, however, only "fixed" can be specified. If an I/O device is selected as a source or destination device, SAC or DAC in the CCRn register must be set to "fixed." If address increase or decrease is selected, the bit position for counting can be specified using SACM or DACM in the DTCRn register. To specify the bit position for counting a source address, SACM must be used, while DACM must be used to specify the bit position for a destination address. Any of the bits 0, 4, 8, 12 and 16 can be specified as the bit position for address counting. If 0 is selected, an address normally increases or decreases. By selecting bits 4, 8, 12 or 16, it is possible to increase or decrease an address irregularly. Examples of address changes are shown below. Example 1: Monotonic increase for a source device and irregular increase for a destination device SAC: Address increase DAC: Address increase TrSiz: Transfer unit 32 bits Source address: 0xA000_1000 Destination address: 0xB000_0000 SACM: 000 counting to begin from bit 0 of the address counter DACM: 001 counting to begin from bit 4 of the address counter Source 0xA000_1000 0xA000_1001 0xA000_1002 0xA000_1003 Destination 0xB000_0000 0xB000_0010 0xB000_0020 0xB000_0030 ... 1st 2nd 3rd 4th ... TMP19A64(rev1.1)-10-22 TMP19A64C1D Example 2: Irregular decrease for a source device and monotonic decrease for a destination device SAC: Address decrease DAC: Address decrease TrSiz: Transfer unit 16 bits Source address: Initial value 0xA000_1000 Destination address: 0xB000_0000 SACM: 010 counting to begin from bit 8 of the address counter DACM: 000 counting to begin from bit 0 of the address counter 1st 2nd 3rd 4th Source 0xA000_1000 0x9FFF_FF00 0x9FFF_FE00 0x9FFF_FD00 ... Destination 0xB000_0000 0xAFFF_FFFE 0xAFFF_FFFC 0xAFFF_FFFA ... 10.4.2 Transfer Request For the DMAC to transfer data, a transfer request must be issued to the DMAC. There are two types of transfer request: an internal transfer request and an external transfer request. Either of these transfer requests can be selected and specified for each channel. Whichever is selected, the DMAC acquires bus control authority and starts to transfer data if the transfer request is generated after the start of channel operation. * Internal transfer request If the Str bit of CCR is set to "1" when the ExR bit of CCRn is "0," a transfer request is generated immediately. This transfer request is called an internal transfer request. The internal transfer request is valid until the channel operation is completed. Therefore, data can be transferred continuously if either of two events shown below does not occur: * A transition to a channel of higher priority * A shift of bus control authority to another bus master of higher priority In the case of the internal transfer request, data can only be transferred from memory to memory. * External transfer request If the ExR bit of CCRn is "1," setting the Str bit of CCR to "1" allows a channel to go into a standby mode. The INTC or an external device then generates the INTDREQn or DREQn signal for this channel to notify the DMAC of a transfer request, and a transfer request is generated. This transfer request is called an external transfer request. In the case of the external transfer request, data can be transferred from memory to memory and between memory and an I/O device. The TMP19A64 recognizes the transfer request signal by detecting the "L" level of the INTDREQn signal or by detecting the falling edge or "L" level of the DREQn signal. The unit of data to be transferred in response to one transfer request is specified in the TrSiz field of CCRn, and 32, 16 or 8 bits can be selected. Transfer requests using INTDREQn and DREQn are described in detail on the next page. TMP19A64(rev1.1)-10-23 TMP19A64C1D A transfer request made by the interrupt controller (INTC) A transfer request made by the interrupt controller is cleared using the DACKn signal. This DACKn signal is asserted only if a bus cycle for an I/O device or the number of bytes (value set in the BCRn register) transferred from memory to memory becomes "0." Therefore, if data is transferred between memory and an I/O device, the amount of data specified by TrSiz is transferred only once because INTDREQn is cleared upon completion of one data transfer from one transfer request. On the other hand, if data is transferred from memory to memory, it can be transferred successively in response to a transfer request because INTDREQn is not cleared until the number of bytes transferred (value set in the BCRn register) becomes "0." Note that if the DMAC acknowledges an interrupt set in INTDREQn and if this interrupt is cleared by the INTC before DMA transfer begins, there is a possibility that DMA transfer might be executed once after the interrupt is cleared, depending on the timing. A transfer request made by an external device External pins (DREQ2 and DREQ3) are internally wired to allow them to function as pins of the port F and port J. These pins can be selected by setting the function control registers PFFC and PJFC to an appropriate setting. If both ports are set to use the DMAC function, the port F is given priority in using the DMAC function. In the edge mode, the DREQn signal must be deasserted and then asserted for each transfer request to create an effective edge. In the level mode, however, successive transfer requests can be recognized by maintaining an effective level. In memory-to-memory transfer, only the "L" level mode can be used. In I/O-to-memory transfer, only the falling edge mode can be used. - Level mode In the level mode, the DMAC detects the "L" level of the DREQn signal upon the rising of the internal system clock. If it detects the "L" level of the DREQn signal when a channel is in a standby mode, it goes into transfer mode and starts to transfer data. To use the DREQn signal at an active level, the PosE bit (bit 13) of the CCRn register must be set to "0." The DACKn signal is active at the "L" level, as in the case of the DREQn signal. If an external circuit asserts the DREQn signal, the DREQn signal must be maintained at the "L" level until the DACKn signal is asserted. If the DREQn signal is deasserted before the DACKn signal is asserted, a transfer request may not be recognized. If the DREQn signal is not at the "L" level, the DMAC judges that there is no transfer request, and starts a transfer operation for other channels or releases bus control authority and goes into a standby mode. The unit of a transfer request is specified in the TrSiz field ( TMP19A64(rev1.1)-10-24 TMP19A64C1D DREQn A[31:1] Transfer data DACKn Fig. 10.4.2.1 Transfer Request Timing (Level Mode) - Edge mode In the edge mode, the DMAC detects the falling edge of the DREQn signal. If it detects the falling edge of the DREQn signal upon the rising of the internal system clock (the case in which the "L" level is detected upon the rising of the system clock although it was not detected upon the rising of the previous system clock) when a channel is in a standby mode, it judges that there is a transfer request, goes into transfer mode, and starts a transfer operation. To detect the falling edge of the DREQn signal, the PosE bit (bit 13) of the CCRn register must be set to "0," and the Lev bit (bit 12) must also be set to "0." The DACKn signal is active at the "L" level. If the falling edge of the DREQn signal is detected after the DACKn signal is asserted, the next data is transferred without a pause. If there is no falling edge of the DREQn signal after the DACKn signal is asserted, the DMAC judges that there is no transfer request, and starts a transfer operation for other channels or goes into a standby mode after releasing bus control authority. The unit of a transfer request is specified in the TrSiz field ( DREQn A[31:1] Transfer data Transfer data DACKn Fig. 10.4.2.2 Transfer Request Timing (Edge Mode) TMP19A64(rev1.1)-10-25 TMP19A64C1D 10.4.3 Address Mode In the address mode, whether the DMAC executes data transfers by outputting addresses to both source and destination devices or it does by outputting addresses to either a source device or a destination device is specified. The former is called the dual address mode, and the latter is called the single address mode. For TMP19A64, only the dual address mode is available. In the dual address mode, The DMAC first performs a read of the source device by storing the data output by the source device in one of its registers (DHR). It then executes a write on the destination device by writing the stored data to the device, thereby completing the data transfer. DMAC Source device Address Address bus Data Data bus Destination device Fig. 10.4.3.1 Basic Concept of Data Transfer in the Dual Address Mode The unit of data to be transferred by the DMAC is the amount of data (32, 16 or 8 bits) specified in the TrSiz field of the CCRn. One unit of data is transferred each time a transfer request is acknowledged. In the dual address mode, the unit of data is read from the source device, put into the DHR and written to the destination device. Access to memory takes place when the specified unit of data is transferred. If access to external memory takes place, 16-bit access takes place twice if the unit of data is set to 32 bits and if the bus width set in the CS wait controller is 16 bits. Likewise, if the unit of data is set to 32 bits and if the bus width set in the CS wait controller is 8 bits, 8-bit access takes place four times. If data is to be transferred from memory to an I/O device or from an I/O device to memory, the unit of data to be transferred must be specified and, at the same time, the bus width of an I/O device (device port size) must be specified in the DPS field of the CCRn (32, 16 or 8 bits). TMP19A64(rev1.1)-10-26 TMP19A64C1D If the unit of data to be transferred is equal to a device port size, a read or write is executed once for an I/O device. If a device port size is smaller than the unit of data to be transferred, the DMAC performs a read or write for an I/O device more than once. For example, if the unit of data to be transferred is 32 bits and if data is transferred from an I/O device whose device port size is 8 bits to memory, 8 bits of data are read from an I/O device four consecutive times and stored in the DHR. This 32-bit data is then written to memory all at once (twice if the data is written to external memory and if the bus width is 16 bits). An address change occurs by the amount defined as the unit of data to be transferred. The BCRn value also changes by the same amount. A device port size must not be larger than the unit of data to be transferred. The relationships between units of data to be transferred and device port sizes are summarized in Table 10.4.3.2. Table 10.4.3.2 Units of Data to Be Transferred and Device Port Sizes (Dual Address Mode) TrSiz 0x (32 bits) 0x (32 bits) 0x (32 bits) 10 (16 bits) 10 (16 bits) 10 (16 bits) 11 (8 bits) 11 (8 bits) 11 (8 bits) DPS 0x (32 bits) 10 (16 bits) 11 (8 bits) 0x (32 bits) 10 (16 bits) 11 (8 bits) 0x (32 bits) 10 (16 bits) 11 (8 bits) Bus operations performed on I/O device Once Twice 4 times Setting prohibited Once Twice Setting prohibited Setting prohibited Once TMP19A64(rev1.1)-10-27 TMP19A64C1D 10.4.4 Channel Operation A channel is activated if the Str bit of the CCRn of a channel is set to "1." If a channel is activated, an activation check is conducted and if no error is detected, the channel is put into a standby mode. If a transfer request is generated when a channel is in a standby mode, the DMAC acquires bus control authority and starts to transfer data. Channel operation is completed either normally or abnormally (forced termination or occurrence of an error). Either normal completion or abnormal completion is indicated to the CSRn. Start of channel operation A channel is activated if the Str bit of the CCRn is set to "1." When a channel is activated, a configuration error check is conducted and if no error is detected, the channel is put into a standby mode. If an error is detected, the channel is deactivated and this state of completion is considered to be abnormal completion. When a channel goes into a standby mode, the Act bit of the CSRn of that channel becomes "1." If a channel is programmed to start operation in response to an internal transfer request, a transfer request is generated immediately and the DMAC acquires bus control authority and starts to transfer data. If a channel is programmed to start operation in response to an external transfer request, the DMAC acquires bus control authority after INTDREQn or DREQn is asserted, and starts to transfer data. Completion of channel operation A channel completes operation either normally or abnormally and either one of these states is indicated to the CSRn. If an attempt is made to set the Str bit of the CCRn register to "1" when the NC or AbC bit of the CSRn register is "1," channel operation does not start and the completion of operation is considered to be abnormal completion. Normal completion Channel operation is considered to have been completed normally in the case shown below. For channel operation to be considered to have been completed normally, the transfer of a unit of data (value specified in the TrSiz field of CCRn) must be completed successfully. * When the contents of BCRn become 0 and data transfer is completed Abnormal completion Cases of abnormal completion of DMAC operation are as follows: * Completion due to a configuration error A configuration error occurs if there is a mistake in the DMA transfer setting. Because a configuration error occurs before data transfer begins, values specified in SARn, DARn and BCRn remain the same as when they were initially specified. If channel operation is completed abnormally due to a configuration error, the AbC bit of the CSRn is set to "1," along with the Conf bit. Causes of a configuration error are as follows: - - - - - - Both SIO and DIO were set to "1." The Str bit of CCRn was set to "1" when the NC bit or AbC bit of CSRn was "1." A value that is not an integer multiple of the unit of data was set for BCRn. A value that is not an integer multiple of the unit of data was set for SARn or DARn. A prohibited combination of a device port size and a unit of data to be transferred was set. The Str bit of CCRn was set to "1" when the BCRn value was "0." TMP19A64(rev1.1)-10-28 TMP19A64C1D * Completion due to a bus error If the DMAC operation has been completed abnormally due to a bus error, the AbC bit of CSRn is set to "1" and the BES or BED bit of CSRn is set to "1." - A bus error was detected during data transfer. (Note) If the DMAC operation has been completed abnormally due to a bus error, BCR, SAR and DAR values cannot be guaranteed. If a bus error persists, refer to 21. "List of Functional Registers" which appear later in this document. 10.4.5 Order of Priority of Channels Concerning the eight channels of the DMAC, the smaller the channel number assigned to each channel, the higher the priority. If a transfer request is generated to channels 0 and 1 simultaneously, a transfer request for channel 0 is processed with higher priority and the transfer operation is performed accordingly. When the transfer request for channel 0 is cleared, the transfer operation for channel 1 is performed if the transfer request still exists (An internal transfer request is retained if it is not cleared. The interrupt controller retains an external transfer request if the active state for an interrupt request assigned to DMA requests in the interrupt controller is set to edge mode. However, the interrupt controller does not retain an external transfer request if the active state is set to level mode. If the active state for an interrupt request assigned to DMA requests in the interrupt controller is set to level mode, it is necessary to continue asserting the interrupt request signal). If a transfer request is generated when data is being transferred through channel 1, a channel transition occurs at channel 0, that is, data transfer through channel 1 is temporarily suspended and data transfer through channel 0 is started. When the transfer request for channel 0 is cleared, data transfer through channel 1 resumes. Channel transitions occur upon the completion of data transfers (when the writing of all data in the DHR has been completed). Interrupts Upon completion of a channel operation, the DMAC can generate interrupt requests (INTDMAn: DMA transfer completion interrupt) to the TX19A processor core with two types of interrupts available: a normal completion interrupt and an abnormal completion interrupt. * Normal completion interrupt If a channel operation is completed normally, the NC bit of CSRn is set to "1." If a normal completion interrupt is authorized for the NIEn bit of the CCRn, the DMAC requests the TX19A processor core to authorize an interrupt. * Abnormal completion interrupt If a channel operation is completed abnormally, the AbC bit of CSRn is set to "1." If an abnormal completion interrupt is authorized for the AbIEn bit of the CCRn, the DMAC requests the TX19A processor core to authorize an interrupt. TMP19A64(rev1.1)-10-29 TMP19A64C1D 10.5 Timing Diagrams DMAC operations are synchronous to the rising edges of the internal system clock. 10.5.1 Dual Address Mode * Memory-to-memory transfer Fig. 10.5.1.1 shows an example of the timing with which 16-bit data is transferred from one external memory (16-bit width) to another (16-bit width). Data is actually transferred successively until BCRn becomes "0." tsys A[23:0] /CS0 /CS1 /RD /WR,/HWR D[15:0] Data Data Read Write Fig. 10.5.1.1 Dual Address Mode (Memory-to-Memory) * Memory-to-I/O device transfer Fig. 10.5.1.2 shows an example of the timing with which data is transferred from memory to an I/O device if the unit of data to be transferred is set to 16 bits and if the device port size is set to 8 bits. tsys A[23:0] /CS0 /CS1 /RD /WR D[15:0] Data Data Data Read Write Write Fig. 10.5.1.2 Dual Address Mode (Memory-to-I/O Device) TMP19A64(rev1.1)-10-30 TMP19A64C1D * I/O device-to-memory transfer Fig. 10.5.1.3 shows an example of the timing with which data is transferred from an I/O device to memory if the unit of data to be transferred is set to 16 bits and if the device port size is set to 8 bits. tsys A[23:0] /CS0 /CS1 /RD /WR D[15:0] Data Data Data Read Read Write Fig. 10.5.1.3 Dual Address Mode (I/O Device-to-Memory) TMP19A64(rev1.1)-10-31 TMP19A64C1D 10.5.2 DREQn-Initiated Transfer Mode * Data transfer from internal RAM to external memory (multiplexed bus, 5-wait insertion, level mode) Fig. 10.5.2.1 shows two timing cycles in which 16-bit data is transferred twice from internal RAM to external memory (16-bit width). (7+) clock (7+) 5 waits 5 Internal system clock /DREQn /DACKn ALE A[23:16] AD[15:0] /RD /WR /HWR /CSn R/W_ Add Add Data Add Data Fig. 10.5.2.1 Level Mode (from Internal RAM to External Memory) * Data transfer from external memory to internal RAM (multiplexed bus, 5-wait insertion, level mode) Fig. 10.5.2.2 shows two timing cycles in which 16-bit data is transferred twice from external memory (16-bit width) to internal RAM. (7+) clock (7+) Internal system clock 5 waits 5 /DREQn /DACKn ALE A[23:16] AD[15:0] /RD /WR /HWR /CSn R/W_ Add Add Data Add Data Fig. 10.5.2.2 Level Mode (from External Memory to Internal RAM) TMP19A64(rev1.1)-10-32 TMP19A64C1D * Data transfer from internal RAM to external memory (separate bus, 5-wait insertion, level mode) Fig. 10.5.2.3 shows two timing cycles in which 16-bit data is transferred twice from internal RAM to external memory (16-bit width). (7+) clock (7+) 5 waits 5 Internal system clock /DREQn /DACKn A[23:0] D[15:0] /RD /WR /HWR /CSn R/W_ Fig. 10.5.2.3 Level Mode (Internal RAM to External Memory) * Data transfer from external memory to internal RAM (separate bus, 5-wait insertion, level mode) Fig. 10.5.2.4 shows two timing cycles in which 16-bit data is transferred twice from external memory (16-bid width) to internal RAM. (7+) clock (7+) Internal system clock 5 waits 5 /DREQn /DACKn A[23:0] D[15:0] /RD /WR /HWR /CSn R/W_ Fig. 10.5.2.4 Level Mode (from External Memory to Internal RAM) TMP19A64(rev1.1)-10-33 TMP19A64C1D * Data transfer from internal RAM to external memory (multiplexed bus, 5-wait insertion, edge mode) Fig. 10.5.2.5 shows one timing cycle in which 16-bit data is transferred once from internal RAM to external memory (16-bit width). (7+) clock (7+) 5 waits 5 Internal system clock /DREQn /DACKn ALE A[23:16] AD[15:0] /RD /WR /HWR /CSn R/W_ Add Add Data Fig. 10.5.2.5 Edge Mode (from Internal RAM to External Memory) * Data transfer from external memory to internal RAM (multiplexed bus, 5-wait insertion, edge mode) Fig. 10.5.2.6 shows one timing cycle in which 16-bit data is transferred once from external memory (16-bit width) to internal RAM. (7+) clock (7+) Internal system clock 5 waits 5 /DREQn /DACKn ALE A[23:16] AD[15:0] /RD /WR /HWR /CSn R/W_ Add Add Data Fig. 10.5.2.6 Edge Mode (from External Memory to Internal RAM) TMP19A64(rev1.1)-10-34 TMP19A64C1D * Data transfer from internal RAM to external memory (separate bus, 5-wait insertion, edge mode) Fig. 10.5.2.7 shows one timing cycle in which 16-bit data is transferred once from internal RAM to external memory (16-bit width). (7+) (7+) clock 5 waits 5 Internal system clock /DREQn /DACKn A[23:0] D[15:0] /RD /WR /HWR /CSn R/W_ Fig. 10.5.2.7 Edge Mode (from Internal RAM to External Memory) * Data transfer from external memory to internal RAM (separate bus, 5-wait insertion, edge mode) Fig. 10.5.2.8 shows one timing cycle in which 16-bit data is transferred once from external memory (16-bit width) to internal RAM. (7+) (7+) clock Internal system clock 5 waits 5 /DREQn /DACKn A[23:0] D[15:0] /RD /WR /HWR /CSn R/W_ Fig. 10.5.2.8 Edge Mode (from External Memory to Internal RAM) TMP19A64(rev1.1)-10-35 TMP19A64C1D 10.6 Case of Data Transfer The settings described below relate to a case in which serial data received (SCnBUF) is transferred to the internal RAM by DMA transfer. DMA (ch.0) is used to transfer data. The DMA0 is activated by a receive interrupt generated by SIO1. IMC4 INTCLR SC1MOD0 SC1CR BR1CR 0xxxxx_xx70 0x40 0x29 0x00 0x1F /* @fc=54MHz, Transfer rate setting */ /* assigned to DMC0 activation factor * / /* IVR [9:4], INTRX1 interrupt factor * / /* UART mode, 8-bit length, baud rate generator * / DCR IMCE INTCLR IMCE DTCR0 SAR0 DAR0 BCR0 CCR0 0x8000_0000 0xxxxx_xx40 0xE0 0xxxxx_xx44 0x0000_0000 0xFFFF_F208 0xFFFF_9800 0x0000_00FF 0x80c0_5B0f /* DMA reset * / /* Disable interrupt setting */ /* IVR [8:0] value * / /* level = 4 (any given value) */ /* DACM = 000 */ /* SACM = 000 */ /* physical address of SC1BUF */ /* physical address of destination to which data is transferred */ /* 256 (number of bytes transferred) / /* DMA ch.0 setting */ TMP19A64(rev1.1)-10-36 TMP19A64C1D 11. 16-bit Timer/Event Counters (TMRBs) Each of the eleven channels (TMRB0 through TMRBA) has a multi-functional, 16-bit timer/event counter. TMRBs operate in the following four operation modes: * * * * 16-bit interval timer mode 16-bit event counter mode 16-bit programmable square-wave output (PPG) mode Two-phase pulse input counter mode (quad-speed and TMRBA) * * * Frequency measurement mode Pulse width measurement mode Time difference measurement mode The use of the capture function allows TMRBs to operate in three other modes: Each channel consists of a 16-bit up-counter, two 16-bit timer registers (one of which is double-buffered), two 16-bit capture registers, two comparators, a capture input control, a timer flip-flop and its associated control circuit. Each channel (TMRB0 through TMRBA) functions independently and while the channels operate in the same way, there are differences in their specifications as shown in Table 11.1 and the two-phase pulse count function. Therefore, the operational descriptions here are for TMRB0 only and for the two-phase pulse count function TMRBA only. TMP19A64(rev1.1)-11-1 TMP19A64C1D Table 11.1 Differences in the Specifications of TMRB Modules Channel Specification External clock/ capture trigger input pins External pins Timer flip-flop output pin Internal signals Timer for capture triggers Timer RUN register Timer control register Timer mode register Timer flip-flop control register Timer status register Timer UC preset register Register names Timer register TMRB0 TB0IN0 (shared with PA0) TB0IN1 (shared with PA1) TMRB1 TB1IN0 (shared with PA3) TB1IN1 (shared with PA4) TMRB2 TMRB3 TMRB4 TMRB5 - - - - TB1OUT TB2OUT TB3OUT TB4OUT TB5OUT TB0OUT (shared with PA2) (shared with PA5) (shared with PA6) (shared with PA7) (shared with PB0) (shared with PB1) TB9OUT TB0RUN TB0CR TB0MOD TB0FFCR TB0ST TB0UCL TB0UCH TB0RG0L TB0RG0H TB0RG1L TB0RG1H TB0CP0L TB0CP0H TB0CP1L TB0CP1H TB9OUT TB1RUN TB1CR TB1MOD TB1FFCR TB1ST TB1UCL TB1UCH TB1RG0L TB1RG0H TB1RG1L TB1RG1H TB1CP0L TB1CP0H TB1CP1L TB1CP1H TB9OUT TB2RUN TB2CR TB2MOD TB2FFCR TB2ST TB2UCL TB2UCH TB2RG0L TB2RG0H TB2RG1L TB2RG1H TB2CP0L TB2CP0H TB2CP1L TB2CP1H TB9OUT TB3RUN TB3CR TB3MOD TB3FFCR TB3ST TB3UCL TB3UCH TB3RG0L TB3RG0H TB3RG1L TB3RG1H TB3CP0L TB3CP0H TB3CP1L TB3CP1H TB9OUT TB4RUN TB4CR TB4MOD TB4FFCR TB4ST TB4UCL TB4UCH TB0RG0L TB4RG0H TB4RG1L TB4RG1H TB4CP0L TB4CP0H TB4CP1L TB4CP1H TB3OUT TB5RUN TB5CR TB5MOD TB5FFCR TB5ST TB5UCL TB5UCH TB5RG0L TB5RG0H TB5RG1L TB5RG1H TB5CP0L TB5CP0H TB5CP1L TB5CP1H Capture register Channel Specification External clock/ capture trigger input pins External pins Timer flip-flop output pin Internal signals Timer for capture triggers Timer RUN register Timer control register Timer mode register Timer flip-flop control register Timer status register Timer UC preset register Register names Timer register TMRB6 TMRB7 TMRB8 TMRB9 TMRBA TBAIN0 (shared with PB6) TBAIN1 (shared with PB7) - TB3OUT TBARUN TBACR TBAMOD TBAFFCR TBAST TBAUCL TBAUCH TBARG0L TBARG0H TBARG1L TBARG1H TBACP0L TBACP0H TBACP1L TBACP1H - - - - TB6OUT TB7OUT TB8OUT TB9OUT (shared with PB2) (shared with PB3) (shared with PB4) (shared with PB5) TB3OUT TB6RUN TB6CR TB6MOD TB6FFCR TB6ST TB6UCL TB6UCH TB6RG0L TB6RG0H TB6RG1L TB6RG1H TB6CP0L TB6CP0H TB6CP1L TB6CP1H TB3OUT TB7RUN TB7CR TB7MOD TB7FFCR TB7ST TB7UCL TB7UCH TB7RG0L TB7RG0H TB7RG1L TB7RG1H TB7CP0L TB7CP0H TB7CP1L TB7CP1H TB3OUT TB8RUN TB8CR TB8MOD TB8FFCR TB8ST TB8UCL TB8UCH TB8RG0L TB8RG0H TB8RG1L TB8RG1H TB8CP0L TB8CP0H TB8CP1L TB8CP1H TB3OUT TB9RUN TB9CR TB9MOD TB9FFCR TB9ST TB9UCL TB9UCH TB9RG0L TB9RG0H TB9RG1L TB9RG1H TB9CP0L TB9CP0H TB9CP1L TB9CP1H Capture register TMP19A64(rev1.1)-11-2 (Note) Internal data bus run/ clear 2 T1 T4 Capture register 0 TB0CP0H/L TB0MOD Capture control Match detection Match detection Prescaler clock: T0 CAPTRG TB0IN0 TB0IN1 11.1 Block Diagram of Each Channel TMRB0 interrupt INTTB0 INTTB01 INTTB91 INTTB00 INTTB90 16-bit comparator (CP0) 16-bit comparator (CP1) Overflow interrupt output Register 0 interrupt Register 1 interrupt TMRB2 through TMRB9 have no external clock and capture trigger input functions. 16-bit timer register TB0RG0H/L 16-bit timer register TB0RG1H/L Fig. 11.1.1 TMRB0 Block Diagram (Same for Channels 1 through 9) TMP19A64(rev1.1)-11-3 TB0RUN 16-bit timer status register TB0ST TMP19A64C1D Internal data bus run/ clear TBARUN Internal data bus (Note) 2 T1 T4 TBAMOD Match detection Prescaler clock : T0 There is no TBAOUT external output. CAPTRG TBAIN0 TBAIN1 Timer flip-flop output TBAOUT Fig. 11.1.2 TMRBA Block Diagram TMP19A64(rev1.1)-11-4 16-bit timer register TBARG0H/L TBARUN Match detection 16-bit comparator (CP1) 16-bit timer register TBARG1H/L Internal data bus Up-and-down interrupt output 16-bit timer status register TBAST Register 0 interrupt output Register 1 interrupt output Underflow interrupt output Overflow interrupt output TMP19A64C1D TMP19A64C1D 11.2 Description of Operations for Each Circuit 11.2.1 Prescaler There is a 5-bit prescaler for acquiring the TMRB0 source clock. The prescaler input clock T0 is fperiph/2, fperiph/4, fperiph/8 or fperiph/16 selected by SYSCR0 TMP19A64(rev1.1)-11-5 TMP19A64C1D Table 11.2.1 Prescaler Output Clock Resolutions @fc = 54MHz Release peripheral clock 5 4 3 Prescaler output clock resolutions T1 fc/2 (0.59 s) fc/2 (0.30 s) fc/2 (0.15 s) fc/22(0.07 s) fc/2 (1.19 s) 6 7 6 5 T4 fc/2 (2.37 s) fc/2 (1.19 s) fc/2 (0.59 s) fc/24(0.30 s) fc/2 (4.74 s) 8 9 T16 fc/2 (9.48 s) fc/28(4.74 s) fc/27(2.37 s) fc/26(1.19 s) fc/210(18.96 s) fc/29(9.48 s) fc/28(4.74 s) fc/27(2.37 s) fc/211(37.93 s) fc/210(18.96 s) fc/29(9.48 s) fc/28(4.74 s) fc/212(75.85 s) fc/211(37.93 s) fc/210(18.96 s) fc/29(9.48 s) fc/29(9.48 s) fc/28(4.74 s) fc/27(2.37 s) fc/26(1.19 s) fc/29(9.48 s) fc/28(4.74 s) fc/27(2.37 s) fc/26(1.19 s) fc/29(9.48 s) fc/28(4.74 s) fc/27(2.37 s) fc/26(1.19 s) fc/29(9.48 s) fc/28(4.74 s) fc/27(2.37 s) fc/26(1.19 s) fc/25(0.59 s) fc/24(0.30 s) fc/2 (0.15 s) 3 fc/27(2.37 s) fc/26(1.19 s) fc/2 (0.59 s) 5 fc/27(2.37 s) fc/26(1.19 s) fc/2 (0.59 s) 5 fc/29(9.48 s) fc/28(4.74 s) fc/2 (2.37 s) 7 fc/24(0.30 s) fc/2 (4.74 s) 8 fc/26(1.19 s) fc/2 (18.96 s) 10 fc/27(2.37 s) fc/26(1.19 s) fc/2 (0.59 s) 5 fc/29(9.48 s) fc/28(4.74 s) fc/2 (2.37 s) 7 fc/25(0.59 s) fc/24(0.30 s) fc/2 (0.15 s) 3 fc/27(2.37 s) fc/26(1.19 s) fc/2 (0.59 s) 5 fc/22(0.07 s) fc/25(0.59 s) fc/2 (0.30 s) 4 fc/24(0.30 s) fc/27(2.37 s) fc/2 (1.19 s) 6 fc/23(0.15 s) fc/25(0.59 s) fc/24(0.30 s) fc/25(0.59 s) fc/25(0.59 s) fc/2 (0.30 s) 4 fc/27(2.37 s) fc/26(1.19 s) fc/2 (0.59 s) 5 fc/24(0.30 s) fc/27(2.37 s) fc/2 (1.19 s) 6 fc/25(0.59 s) (Note 1) The prescaler output clock Tn must be selected so that Tn TMP19A64C1D 11.2.2 Up-counter (UC0) and Up-counter Capture Registers (TB0UCL, TB0UCH) This is the 16-bit binary counter that counts up in response to the input clock specified by TB0MOD If UC0 overflow occurs, the INTTB01 overflow interrupt is generated. TMRBA have the two-phase pulse input count function. The two-phase pulse count mode is activated by TBARUN 11.2.3 Timer Registers (TB0RG0H/L, TB0RG1H/L) These are 16-bit registers for specifying counter values and two registers are built into each channel. If a value set on this timer register matches that on a UC0 up-counter, the match detection signal of the comparator becomes active. To write data to the TB0RG0H/L and TB0RG1H/L timer registers, either a 2-byte data transfer instruction or a 1-byte data transfer instruction written twice in the order of low-order 8 bits followed by high-order 8 bits can be used. TB0RG0 of this timer register is paired with register buffer 0 - a double-buffered configuration. TB0RG0 uses TB0RUN TMP19A64(rev1.1)-11-7 TMP19A64C1D 11.2.4 Capture Registers (TB0CP0H/L, TB0CP1H/L) To read data from the capture register, use 1-byte data transfer instruction twice and make sure that reading is performed in the order of low-order bits followed by high-order bits. (Don't use 2-byte transfer instruction for data reading.) 11.2.5 Capture This is a circuit that controls the timing of latching values from the UC0 up-counter into the TB0CP0 and TB0CP1 capture registers. The timing with which to latch data is specified by TB0MOD 11.2.6 Comparators (CP0, CP1) These are 16-bit comparators for detecting a match by comparing set values of the UC0 up-counter with set values of the TB0RG0 and TB0RG1 timer registers. If a match is detected, INTTB0 is generated. 11.2.7 Timer Flip-flop (TB0FF0) The timer flip-flop (TB0FF0) is reversed by a match signal from the comparator and a latch signal to the capture registers. It can be enabled or disabled to reverse by setting the TB0FFCR TMP19A64(rev1.1)-11-8 TMP19A64C1D 11.3 Register Description TMRBn RUN register (n=0 through 9) 7 TBnRUN (0xFFFF_F1x0) bit Symbol Read/Write After reset TBnRDE R/W R/W R/W R/W 6 5 4 3 I2TBn R/W 2 TBnPRU N R/W 0 1 0 TBnRUN R 0 R/W 0 Function Double Buffering 0: Disable 1: Enable Write "0." Write "0." Write "0." IDLE 0: Stop 1: Operate Timer Run/Stop Control 0: Stop & clear 1: Count * The first bit can be read as "0." |